DG534ADN-E3 Vishay

DG534A/538A Vishay Siliconix 4-/8-Channel Wideband Video Multiplexers Wide Bandwidth: 500 MHz Improved System Bandwidth Wideband Signal Routing and Multiplexing Very Low Crosstalk: 97 dB 5 MHz Improved Channel Off-Isolation Video Switchers On-Board TTL-Compatible Latches with Simplified Logic Interfacing Readback ATE Systems High-Speed Readback Optional Negative Supply Infrared Imaging Allows Bipolar Signal Swings Ultrasound Imaging Low r : 45 DS(on) Reduced Insertion Loss Single-Ended or Differential Operation Allows Differential Signal Switching Latch-up Proof The DG534A is a digitally selectable 4-channel or dual The DG534A/DG538A are built on a D/CMOS process that 2-channel multiplexer. The DG538A is an 8-channel or dual combines n-channel DMOS switching FETs with low-power 4-channel multiplexer. On-chip TTL-compatible address CMOS control logic, drivers and latches. The low-capacitance decoding logic and latches with data readback are included to DMOS FETs are connected in a T configuration to achieve simplify the interface to a microprocessor data bus. The low extremely high levels of off isolation. Crosstalk is reduced to on-resistance and low capacitance of the these devices make 97 dB at 5 MHz by including a ground line between adjacent them ideal for wideband data multiplexing and video and audio signal paths. An epitaxial layer prevents latch-up. signal routing in channel selectors and crosspoint arrays. An optional negative supply pin allows the handling of bipolar signals without dc biasing. For more information refer to Vishay Siliconix applications note AN502. DG534ADJ DG534ADN Dual-In-Line PLCC GND 1 20 NC D D 2 19 312 1 209 A B V+ 3 18 V S 4 18 S S S A1 B1 4 17 A1 B1 GND 5 17 GND GND 5 16 GND S 6 16 S A2 B2 S S 6 15 A2 B2 4/2 7 15 V L 4/2 7 14 V L RS 8 14 NC Latch/Drivers RS I/O 8 13 Latches/Drivers WR912 EN 9110 11 123 A A 10 11 1 0 Top View Top View Document Number: 70069 www.vishay.com S-05734Rev. G, 29-Jan-02 1 WR V+ A D 1 A A GND 0 EN D B I/O VDG534A/538A Vishay Siliconix DG538ADJ Dual-In-Line DG538ADN 1 28 PLCC GND D B 2 27 D V A 3 26 V+ S 4 3 2 1 28 27 26 B1 4 25 S GND A1 5 24 GND S B2 5 25 GND GND 6 23 S 6 24 S S GND A2 A2 B2 7 23 GND GND 7 22 GND S B3 8 22 S S A3 B3 8 21 S GND A3 9 21 GND GND 920 GND S B4 S 10 20 S A4 B4 10 19 S V A4 L 8/4 11 19 V L 11 18 Latch/Drivers 8/4 I/O 12 17 RS EN 12 13 14 15 16 17 18 Latch/Drivers 13 16 WR A 0 14 15 A A 2 1 Top View Top View a I/O A A EN WR RS 4/2 On Switch 1 0 X X X X 1 1 Maintains previous state X X X X X 0 X None (latches cleared) X X X 0 0 1 X None 0 0 0 1 0 1 0 S A1 0 0 1 1 0 1 0 S A2 DD and D and D may be may be AA BB connected externally 0 1 0 1 0 1 0 S B1 Latches Transparent 0 1 1 1 0 1 0 S B2 0 X 0 1 0 1 1 S and S A1 B1 0 X 1 1 0 1 1 S and S A2 B2 1 Note b 1 1 Note c Logic 0 = V 0.8 V AL Logic 1 = V 2.4 V AH X = Dont Care Document Number: 70069 www.vishay.com S-05734Rev. G, 29-Jan-02 2 S RS A1 V+ WR A D 2 A A GND 1 A D 0 B EN V S I/O B1