DG604E www.vishay.com Vishay Siliconix 0.3 pC Charge Injection, 100 pA Leakage CMOS 5 V / 5 V / 3 V 4-Channel Multiplexer DESCRIPTION FEATURES The DG604E is an analog 4-channel CMOS, multiplexer, Ultra low charge injection designed to operate from a +3 V to +16 V single supply, or (less than 0.4 pC, typ. over the full analog from 3 V to 8 V, dual supplies. The DG604E is fully signal range) specified at +3 V, +5 V and 5 V. Leakage current < 0.5 nA max. at 85 C The DG604E offers ultralow charge injection less than (for DG604EEQ-T1-GE4) 0.4 pC over the entire signal range and leakage currents of Low switch capacitance (C , 4.2 pF typ.) S(off) 16 pA typical at 25 C. It offers on resistance of 64 typ., Fully specified with single supply operation at 3 V, 5 V, and and low parasitic capacitance of 4.2 pF source off, and dual supplies at 5 V 11 pF Drain on. The part is ideal for analog front end, data CMOS / TTL compatible acquisition and sample and hold designs providing fast and precision signal switching. 414 MHz, -3 dB bandwidth The DG604E switches one of four inputs to a common Excellent isolation and crosstalk performance output as determined by the 3-bit binary address lines: A0, (typ. > -60 dB at 10 MHz) A1, and EN. Each switch conducts equally well in both Fully specified from -40 C to +85 C and -40 C to +125 C directions when on, blocks input voltages up to the supply 14 pin TSSOP and 16 pin miniQFN package level when off, and exhibits break before make switching (1.8 mm x 2.6 mm) action. Material categorization: for definitions of compliance All control logic inputs have guaranteed 2 V logic high limits please see www.vishay.com/doc 99912 when operating from +5 V or 5 V supplies and 1.4 V when operating from a 3 V supply. APPLICATIONS The DG604E operating temperature range is specified from Data acquisition systems -40 C to +125 C. It is available in 14 lead TSSOP and the Medical instruments space saving 1.8 mm x 2.6 mm miniQFN package. Precision instruments Communications systems Automated test equipment Sample and hold circuit Relay replacement FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION DG604E DG604E TSSOP14 mQFN-16 6 A0 NC NC A1 14 A1 A0 1 16 15 14 13 2 13 GND ENABLE Logic ENABLE 1 Logic 12 GND V- 12 3 V+ V- 2 11 V+ 4 S1 11 S3 S1 3 10 S3 Rxx S2 5 10 S4 S2 4 9 S4 6 9 D NC Pin 1 5 6 7 8 Device Marking: Rxx for DG604E 7 NC 8 NC (miniQFN16) D NC NC NC xx = Date/Lot Traceability Code Top View Top View S17-1098-Rev. A, 17-Jul-17 Document Number: 75612 1 For technical questions, contact: analogswitchtechsupport vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000 DG604E www.vishay.com Vishay Siliconix TRUTH TABLE SELECTED INPUT ON SWITCHES ENABLE INPUT A1 A0 DG604E L X X All switches open HL L D to S1 HL H D to S2 HH L D to S3 HH H D to S4 ORDERING INFORMATION TEMP. RANGE PACKAGE PART NUMBER 14 pin TSSOP DG604EEQ-T1-GE4 a -40 C to +125 C 16 pin miniQFN DG604EEN-T1-GE4 Note a. -40 C to +85 C datasheet limits apply ABSOLUTE MAXIMUM RATINGS (T = 25 C, unless otherwise noted) A PARAMETER LIMIT UNIT V+ to V- -0.3 to +18 GND to V- 18 V (V-) -0.3 to (V+) + 0.3 or 30 mA, V , V S D whichever occurs first a Digital inputs (GND) -0.3 to (V+) + 0.3 Continuous current (any terminal) 30 mA Peak current, S or D (pulsed 1 ms, 10 % duty cycle) 100 Storage temperature -65 to +150 C c 14 pin TSSOP 450 b Power dissipation (package) mW d, e 16 pin miniQFN 525 14 pin TSSOP 178 b Thermal resistance (package) C/W 16 pin miniQFN 152 ESED / HBM EIA / JESD22-A114-A 2K V ESD / CDM EIA / JESD22-C101-A 1K Latch up JESD78 300 mA Notes a. Signals on S , D , or IN exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings X X X b. All leads welded or soldered to PC board c. Derate 5.6 mW/C above 70 C d. Derate 6.6 mW/C above 70 C e. Manual soldering with iron is not recommended for leadless components. The miniQFN-16 is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper lip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection S17-1098-Rev. A, 17-Jul-17 Document Number: 75612 2 For technical questions, contact: analogswitchtechsupport vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000