New Product SiE876DF Vishay Siliconix N-Channel 60-V (D-S) MOSFET FEATURES PRODUCT SUMMARY Halogen-free According to IEC 61249-2-21 I (A) D Definition Silicon Package TrenchFET Power MOSFET V (V) R () Q (Typ.) Limit Limit DS DS(on) g Ultra Low Thermal Resistance Using Top- 0.0061 at V = 10 V 60 110 60 51 nC Exposed PolarPAK Package for Double- GS Sided Cooling Leadframe-Based New Encapsulated Package Package Drawing: - Die Not Exposed www.vishay.com/doc 72945 - Same Layout Regardless of Die Size < 150 V Low Q /Q Ratio Helps Prevent Shoot-Through gd gs PolarPAK 100 % R and UIS Tested 10 9 8 7 6 g D G S S D 67 8 9 10 Compliant to RoHS directive 2002/95/EC APPLICATIONS D Primary Side Switch Half-Bridge D DS G D G D G S S D 5 432 1 1 2 3 4 5 S Top View Bottom View Top surface is connected to pins 1, 5, 6, and 10 N-Channel MOSFET For Related Documents: Ordering Information: SiE876DF-T1-GE3 (Lead (Pb)-free and Halogen-free) www.vishay.com/ppg 64823 ABSOLUTE MAXIMUM RATINGS T = 25 C, unless otherwise noted A Parameter Symbol Limit Unit Drain-Source Voltage V 60 DS V V Gate-Source Voltage 20 GS 110 (Silicon Limit) T = 25 C C a 60 (Package Limit) Continuous Drain Current (T = 150 C) I a T = 70 C J D C 60 b, c T = 25 C 22 A b, c T = 70 C A A 17.9 Pulsed Drain Current I 60 DM a T = 25 C C 60 Continuous Source-Drain Diode Current I S b, c T = 25 C A 4.3 Single Pulse Avalanche Current I 50 AS L = 0.1 mH E Single Pulse Avalanche Energy 125 mJ AS T = 25 C 125 C T = 70 C 80 C P Maximum Power Dissipation W D b, c T = 25 C A 5.2 b, c T = 70 C A 3.3 T , T Operating Junction and Storage Temperature Range - 55 to 150 J stg C d, e Soldering Recommendations (Peak Temperature) 260 Notes: a. Package limited. b. Surface Mounted on 1 x 1 FR4 board. c. t = 10 s. ). The PolarPAK is a leadless package. The end of the lead terminal is exposed copper (not d. See Solder Profile (www.vishay.com/ppg 73257 plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection. e. Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components. Document Number: 64823 www.vishay.com S09-0862-Rev. A, 18-May-09 1New Product SiE876DF Vishay Siliconix THERMAL RESISTANCE RATINGS Parameter Symbol TypicalMaximumUnit a, b R t 10 s 20 24 Maximum Junction-to-Ambient thJA R (Drain) Maximum Junction-to-Case (Drain Top) 0.8 1 C/W thJC Steady State a, c R (Source) 2.2 2.7 Maximum Junction-to-Case (Source) thJC Notes: a. Surface Mounted on 1 x 1 FR4 board. b. Maximum under Steady State conditions is 68 C/W. c. Measured at source pin (on the side of the package). SPECIFICATIONS T = 25 C, unless otherwise noted J Parameter Symbol Test Conditions Min. Typ.Max.Unit Static Drain-Source Breakdown Voltage V V = 0 V, I = 250 A 60 V DS GS D V Temperature Coefficient V /T 70 DS DS J I = 250 A mV/C D V Temperature Coefficient V /T - 9 GS(th) GS(th) J V Gate-Source Threshold Voltage V = V , I = 250 A 2.5 4.4 V GS(th) DS GS D I Gate-Source Leakage V = 0 V, V = 20 V 100 nA GSS DS GS V = 60 V, V = 0 V 1 DS GS I Zero Gate Voltage Drain Current A DSS V = 60 V, V = 0 V, T = 55 C 10 DS GS J a I V 5 V, V = 10 V 25 A D(on) On-State Drain Current DS GS a R V = 10 V, I = 20 A 0.0050 0.0061 Drain-Source On-State Resistance DS(on) GS D a g V = 15 V, I = 20 A 30 S Forward Transconductance fs DS D b Dynamic C Input Capacitance 3100 iss C V = 30 V, V = 0 V, f = 1 MHz Output Capacitance 480 pF oss DS GS C Reverse Transfer Capacitance 180 rss Total Gate Charge Q 51 77 g Q V = 30 V, V = 10 V, I = 19.8 A Gate-Source Charge 19 nC gs DS GS D Q Gate-Drain Charge 15 gd R Gate Resistance f = 1 MHz 1.1 2.2 g t Turn-On Delay Time 22 30 d(on) t Rise Time V = 30 V, R = 3 10 15 r DD L ns t I 10 A, V = 10 V, R = 1 Turn-Off Delay Time 25 40 d(off) D GEN g t Fall Time 10 15 f Drain-Source Body Diode Characteristics I Continuous Source-Drain Diode Current T = 25 C 60 S C A a I 60 Pulse Diode Forward Current SM V Body Diode Voltage I = 10 A 0.8 1.2 V SD S t Body Diode Reverse Recovery Time 60 90 ns rr Q Body Diode Reverse Recovery Charge 135 205 nC rr I = 10 A, dI/dt = 100 A/s, T = 25 C F J t Reverse Recovery Fall Time 42 a ns t Reverse Recovery Rise Time 18 b Notes: a. Pulse test pulse width 300 s, duty cycle 2 % b. Guaranteed by design, not subject to production testing. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. www.vishay.com Document Number: 64823 2 S09-0862-Rev. A, 18-May-09