VS-P100 Series www.vishay.com Vishay Semiconductors Power Modules, Passivated Assembled Circuit Elements, 25 A FEATURES Glass passivated junctions for greater reliability Electrically isolated base plate Available up to 1200 V /V RRM DRM High dynamic characteristics Wide choice of circuit configurations Simplified mechanical design and assembly UL E78996 approved Material categorization: for definitions of compliance PACE-PAK (D-19) please see www.vishay.com/doc 99912 DESCRIPTION The VS-P100 series of integrated power circuits consists of PRIMARY CHARACTERISTICS power thyristors and power diodes configured in a single I 25 A O package. With its isolating base plate, mechanical designs Type Modules - thyristor, standard are greatly simplified giving advantages of cost reduction and reduced size. Package PACE-PAK (D-19) Applications include power supplies, control circuits and battery chargers. MAJOR RATINGS AND CHARACTERISTICS SYMBOL CHARACTERISTICS VALUES UNITS I 85 C 25 A O 50 Hz 357 I A TSM 60 Hz 375 50 Hz 637 2 2 I t A s 60 Hz 580 2 2 I t 6365 A s V , V 400 to 1200 V DRM RRM V 2500 V ISOL T Range -40 to +125 C J T -40 to +125 C Stg ELECTRICAL SPECIFICATIONS VOLTAGE RATINGS V /V , MAXIMUM V , MAXIMUM RRM DRM RSM I MAXIMUM RRM REPETITIVE PEAK REVERSE AND NON-REPETITIVE PEAK TYPE NUMBER AT T MAXIMUM J PEAK OFF-STATE VOLTAGE REVERSE VOLTAGE mA V V VS-P101, VS-P121, VS-P131 400 500 VS-P102, VS-P122, VS-P132 600 700 VS-P103, VS-P123, VS-P133 800 900 10 VS-P103, VS-P124, VS-P134 1000 1100 VS-P105, VS-P125, VS-P135 1200 1300 Revision: 27-Jul-2018 Document Number: 93754 1 For technical questions within your region: DiodesAmericas vishay.com, DiodesAsia vishay.com, DiodesEurope vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000VS-P100 Series www.vishay.com Vishay Semiconductors ON-STATE CONDUCTION PARAMETER SYMBOL TEST CONDITIONS VALUESUNITS 25 A Maximum DC output current at case I Full bridge O temperature 85 C t = 10 ms 357 No voltage reapplied t = 8.3 ms 375 Maximum peak, one-cycle non-repetitive I , TSM A on-state or forward current I FSM t = 10 ms 300 100 % V RRM reapplied t = 8.3 ms 315 Sinusoidal half wave, initial T = T maximum J J t = 10 ms 637 No voltage reapplied t = 8.3 ms 580 2 2 2 Maximum I t for fusing I t A s t = 10 ms 450 100 % V RRM reapplied t = 8.3 ms 410 t = 0.1 ms to 10 ms, no voltage reapplied 2 2 2 Maximum I t for fusing I t 6365 A s 2 2 I t for time tx = I t tx Maximum value of threshold voltage V T = 125 C 0.82 V T(TO) J Maximum level value of on-state slope 2 r T = 125 C, average power = V x I + r + (I ) 12 m t1 J T(TO) T(AV) t T(RMS) resistance Maximum on-state voltage drop V I = x I T = 25 C 1.35 V TM TM T(AV) J Maximum forward voltage drop V I = x I T = 25 C 1.35 V FM FM F(AV) J Maximum non-repetitive rate of rise of T = 125 C from 0.67 V J DRM dI/dt 200 A/s turned-on current I = x I , I = 500 mA, t < 0.5 s, t > 6 s TM T(AV) g r p Maximum holding current I T = 25 C anode supply = 6 V, resistive load, gate open 130 H J mA Maximum latching current I T = 25 C anode supply = 6 V, resistive load 250 L J BLOCKING PARAMETER SYMBOL TEST CONDITIONS VALUESUNITS Maximum critical rate of rise of off-state dV/dt T = 125 C, exponential to 0.67 V gate open 200 V/s J DRM voltage Maximum peak reverse and off-state I , RRM T = 125 C, gate open circuit 10 mA J leakage current at V , V I RRM DRM DRM Maximum peak reverse leakage current I T = 25 C 100 A RRM J 50 Hz, circuit to base, all terminals shorted, RMS isolation voltage V 2500 V ISOL T = 25 C, t = 1 s J TRIGGERING PARAMETER SYMBOL TEST CONDITIONS VALUES UNITS Maximum peak gate power P 8 GM W Maximum average gate power P 2 G(AV) Maximum peak gate current I 2A GM Maximum peak negative gate voltage -V 10 V GM T = -40 C 3 J Maximum gate voltage required to trigger V T = 25 C 2 V GT J T = 125 C 1 J Anode supply = 6 V resistive load T = -40 C 90 J Maximum gate current required to trigger I T = 25 C 60 mA GT J T = 125 C 35 J Maximum gate voltage that will not trigger V 0.2 V GD T = 125 C, rated V applied J DRM Maximum gate current that will not trigger I 2mA GD Revision: 27-Jul-2018 Document Number: 93754 2 For technical questions within your region: DiodesAmericas vishay.com, DiodesAsia vishay.com, DiodesEurope vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000