VS-P400 Series www.vishay.com Vishay Semiconductors Power Modules, Passivated Assembled Circuit Elements, 40 A FEATURES Glass passivated junctions for greater reliability Electrically isolated base plate Available up to 1200 V /V RRM DRM High dynamic characteristics Wide choice of circuit configurations Simplified mechanical design and assembly UL E78996 approved PACE-PAK (D-19) Material categorization: for definitions of compliance please see www.vishay.com/doc 99912 PRIMARY CHARACTERISTICS DESCRIPTION I 40 A O The VS-P400 series of integrated power circuits consists of Type Modules - thyristor, standard power thyristors and power diodes configured in a single package. With its isolating base plate, mechanical designs Package PACE-PAK (D-19) are greatly simplified giving advantages of cost reduction and reduced size. Applications include power supplies, control circuits and battery chargers. MAJOR RATINGS AND CHARACTERISTICS SYMBOL CHARACTERISTICS VALUES UNITS I 80 C 40 A O 50 Hz 385 I , TSM A I FSM 60 Hz 400 50 Hz 745 2 2 I t A s 60 Hz 680 2 2 I t 7450 A s V Range 400 to 1200 V RRM V 2500 V ISOL T J -40 to +125 C T Stg ELECTRICAL SPECIFICATIONS VOLTAGE RATINGS V /V , MAXIMUM V , MAXIMUM RRM DRM RSM I MAXIMUM RRM REPETITIVE PEAK REVERSE AND NON-REPETITIVE PEAK TYPE NUMBER AT T MAXIMUM J PEAK OFF-STATE VOLTAGE REVERSE VOLTAGE mA V V VS-P401, VS-P421, VS-P431 400 500 VS-P402, VS-P422, VS-P432 600 700 VS-P403, VS-P423, VS-P433 800 900 10 VS-P404, VS-P424, VS-P434 1000 1100 VS-P405, VS-P425, VS-P435 1200 1300 Revision: 27-Jul-2018 Document Number: 93755 1 For technical questions within your region: DiodesAmericas vishay.com, DiodesAsia vishay.com, DiodesEurope vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000VS-P400 Series www.vishay.com Vishay Semiconductors ON-STATE CONDUCTION PARAMETER SYMBOL TEST CONDITIONS VALUESUNITS 40 A Maximum DC output current I Full bridge circuits O at case temperature 80 C t = 10 ms 385 No voltage Maximum peak, one-cycle reapplied t = 8.3 ms 400 I , TSM non-repetitive on-state or A I FSM t = 10 ms 325 100 % V forward current RRM reapplied t = 8.3 ms 340 Sinusoidal half wave, initial T = T maximum t = 10 ms J J 745 No voltage reapplied t = 8.3 ms 680 2 2 2 Maximum I t for fusing I t A s t = 10 ms 530 100 % V RRM t = 8.3 ms reapplied 480 t = 0.1 ms to 10 ms, no voltage reapplied 2 2 2 Maximum I t for fusing I t 7450 A s 2 2 I t for time tx = I t tx Low level value of threshold voltage V (16.7 % x x I < I < x I ), T = T maximum 0.83 T(TO)1 T(AV) T(AV) J J V High level value of threshold voltage V (I > x I ), T = T maximum 1.03 T(TO)2 T(AV) J J Low level value of on-state slope resistance r (16.7 % x x I < I < x I ), T = T maximum 9.61 t1 T(AV) T(AV) J J m High level value of on-state slope resistance r (I > x I ), T = T maximum 7.01 t2 T(AV) J J Maximum on-state voltage drop V I = x I T = 25 C 1.4 V TM TM T(AV) J Maximum forward voltage drop V I = x I T = 25 C 1.4 V FM FM F(AV) J Maximum non-repetitive rate of rise of T = 125 C from 0.67 V J DRM dI/dt 200 A/s turned-on current I = x I , I = 500 mA, t < 0.5 s, t > 6 s TM T(AV) g r p Maximum holding current I 130 H T = 25 C anode supply = 6 V, resistive load mA J Maximum latching current I 250 L BLOCKING PARAMETER SYMBOL TEST CONDITIONS VALUESUNITS Maximum critical rate of rise of dV/dt T = 125 C, exponential to 0.67 V gate open 200 V/s J DRM off-state voltage Maximum peak reverse and off-state I , RRM T = 125 C, gate open circuit 10 mA J leakage current at V , V I RRM DRM DRM Maximum peak reverse leakage current I T = 25 C 100 A RRM J 50 Hz, circuit to base, all terminals shorted, RMS isolation voltage V 2500 V ISOL T = 25 C, t = 1 s J TRIGGERING PARAMETER SYMBOL TEST CONDITIONS VALUESUNITS Maximum peak gate power P 8 GM W Maximum average gate power P 2 G(AV) Maximum peak gate current I 2A GM Maximum peak negative gate voltage -V 10 V GM T = - 40 C 3 J Maximum gate voltage required to trigger V T = 25 C 2 V GT J T = 125 C 1 J Anode supply = 6 V resistive load T = - 40 C 90 J Maximum gate current required to trigger I T = 25 C 60 mA GT J T = 125 C 35 J Maximum gate voltage that will not trigger V 0.2 V GD T = 125 C, rated V applied J DRM Maximum gate current that will not trigger I 2mA GD Revision: 27-Jul-2018 Document Number: 93755 2 For technical questions within your region: DiodesAmericas vishay.com, DiodesAsia vishay.com, DiodesEurope vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000