W632GG8NB 32M 8 BANKS 8 BIT DDR3 SDRAM Table of Contents- 1. GENERAL DESCRIPTION ................................................................................................................... 5 2. FEATURES ........................................................................................................................................... 5 3. ORDER INFORMATION ....................................................................................................................... 6 4. KEY PARAMETERS ............................................................................................................................. 7 6. BALL CONFIGURATION ...................................................................................................................... 9 7. BALL DESCRIPTION .......................................................................................................................... 10 8. BLOCK DIAGRAM .............................................................................................................................. 12 9. FUNCTIONAL DESCRIPTION ............................................................................................................ 13 9.1 Basic Functionality .............................................................................................................................. 13 9.2 RESET and Initialization Procedure .................................................................................................... 13 9.2.1 Power-up Initialization Sequence ..................................................................................... 13 9.2.2 Reset Initialization with Stable Power .............................................................................. 15 9.3 Programming the Mode Registers ....................................................................................................... 16 9.3.1 Mode Register MR0 ......................................................................................................... 18 9.3.1.1 Burst Length, Type and Order ................................................................................ 18 9.3.1.2 CAS Latency........................................................................................................... 19 9.3.1.3 Test Mode............................................................................................................... 19 9.3.1.4 DLL Reset............................................................................................................... 19 9.3.1.5 Write Recovery ....................................................................................................... 20 9.3.1.6 Precharge PD DLL ................................................................................................. 20 9.3.2 Mode Register MR1 ......................................................................................................... 20 9.3.2.1 DLL Enable/Disable ................................................................................................ 21 9.3.2.2 Output Driver Impedance Control ........................................................................... 21 9.3.2.3 ODT RTT Values .................................................................................................... 21 9.3.2.4 Additive Latency (AL) ............................................................................................. 21 9.3.2.5 Write leveling .......................................................................................................... 21 9.3.2.6 Output Disable ........................................................................................................ 22 9.3.2.7 TDQS, TDQS ........................................................................................................ 22 9.3.3 Mode Register MR2 ......................................................................................................... 23 9.3.3.1 Partial Array Self Refresh (PASR) .......................................................................... 24 9.3.3.2 CAS Write Latency (CWL) ...................................................................................... 24 9.3.3.3 Auto Self Refresh (ASR) and Self Refresh Temperature (SRT) ............................. 24 9.3.3.4 Dynamic ODT (Rtt WR) ......................................................................................... 24 9.3.4 Mode Register MR3 ......................................................................................................... 25 9.3.4.1 Multi Purpose Register (MPR) ................................................................................ 25 9.4 No OPeration (NOP) Command .......................................................................................................... 26 9.5 Deselect Command ............................................................................................................................. 26 9.6 DLL-off Mode ...................................................................................................................................... 26 9.7 DLL on/off switching procedure ........................................................................................................... 27 9.7.1 DLL on to DLL off Procedure ....................................................................................... 27 9.7.2 DLL off to DLL on Procedure ....................................................................................... 28 9.8 Input clock frequency change ............................................................................................................. 29 9.8.1 Frequency change during Self-Refresh............................................................................ 29 9.8.2 Frequency change during Precharge Power-down .......................................................... 29 9.9 Write Leveling ..................................................................................................................................... 31 Publication Release Date: Apr. 10, 2019 Revision: A02 - 1 - W632GG8NB 9.9.1 DRAM setting for write leveling & DRAM termination function in that mode .................... 32 9.9.2 Write Leveling Procedure ................................................................................................. 32 9.9.3 Write Leveling Mode Exit ................................................................................................. 34 9.10 Multi Purpose Register ........................................................................................................................ 35 9.10.1 MPR Functional Description ............................................................................................. 36 9.10.2 MPR Register Address Definition ..................................................................................... 37 9.10.3 Relevant Timing Parameters ............................................................................................ 37 9.10.4 Protocol Example ............................................................................................................. 37 9.11 ACTIVE Command .............................................................................................................................. 43 9.12 PRECHARGE Command .................................................................................................................... 43 9.13 READ Operation ................................................................................................................................. 44 9.13.1 READ Burst Operation ..................................................................................................... 44 9.13.2 READ Timing Definitions .................................................................................................. 45 9.13.2.1 READ Timing Clock to Data Strobe relationship .................................................... 46 9.13.2.2 READ Timing Data Strobe to Data relationship ..................................................... 47 9.13.2.3 tLZ(DQS), tLZ(DQ), tHZ(DQS), tHZ(DQ) Calculation ............................................. 48 9.13.2.4 tRPRE Calculation .................................................................................................. 49 9.13.2.5 tRPST Calculation .................................................................................................. 49 9.13.2.6 Burst Read Operation followed by a Precharge...................................................... 55 9.14 WRITE Operation ................................................................................................................................ 57 9.14.1 DDR3 Burst Operation ..................................................................................................... 57 9.14.2 WRITE Timing Violations ................................................................................................. 57 9.14.2.1 Motivation ............................................................................................................... 57 9.14.2.2 Data Setup and Hold Violations .............................................................................. 57 9.14.2.3 Strobe to Strobe and Strobe to Clock Violations ..................................................... 57 9.14.2.4 Write Timing Parameters ........................................................................................ 57 9.14.3 Write Data Mask............................................................................................................... 58 9.14.4 tWPRE Calculation........................................................................................................... 59 9.14.5 tWPST Calculation ........................................................................................................... 59 9.15 Refresh Command .............................................................................................................................. 66 9.16 Self-Refresh Operation ....................................................................................................................... 68 9.17 Power-Down Modes ............................................................................................................................ 70 9.17.1 Power-Down Entry and Exit ............................................................................................. 70 9.17.2 Power-Down clarifications - Case 1 ................................................................................. 76 9.17.3 Power-Down clarifications - Case 2 ................................................................................. 76 9.17.4 Power-Down clarifications - Case 3 ................................................................................. 77 9.18 ZQ Calibration Commands .................................................................................................................. 78 9.18.1 ZQ Calibration Description ............................................................................................... 78 9.18.2 ZQ Calibration Timing ...................................................................................................... 79 9.18.3 ZQ External Resistor Value, Tolerance, and Capacitive loading ...................................... 79 9.19 On-Die Termination (ODT) .................................................................................................................. 80 9.19.1 ODT Mode Register and ODT Truth Table ...................................................................... 80 9.19.2 Synchronous ODT Mode .................................................................................................. 81 9.19.2.1 ODT Latency and Posted ODT ............................................................................... 81 9.19.2.2 Timing Parameters ................................................................................................. 81 9.19.2.3 ODT during Reads .................................................................................................. 83 9.19.3 Dynamic ODT .................................................................................................................. 84 9.19.3.1 Functional Description: ........................................................................................... 84 9.19.3.2 ODT Timing Diagrams ............................................................................................ 85 Publication Release Date: Apr. 10, 2019 Revision: A02 - 2 -