X-On Electronics has gained recognition as a prominent supplier of W948D6FBHX6E DRAM across the USA, India, Europe, Australia, and various other global locations. W948D6FBHX6E DRAM are a product manufactured by Winbond. We provide cost-effective solutions for DRAM, ensuring timely deliveries around the world.

W948D6FBHX6E Winbond

W948D6FBHX6E electronic component of Winbond
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Part No.W948D6FBHX6E
Manufacturer: Winbond
Category: DRAM
Description: DRAM 256Mb LPDDR, x16, 166MHz, 65nm
Datasheet: W948D6FBHX6E Datasheet (PDF)
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

312: USD 3.1307 ea
Line Total: USD 976.78

Availability - 0
MOQ: 312  Multiples: 312
Pack Size: 312
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0
Ship by Wed. 31 Jul to Fri. 02 Aug
MOQ : 312
Multiples : 312
312 : USD 3.1307
624 : USD 2.885

   
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We are delighted to provide the W948D6FBHX6E from our DRAM category, at competitive rates not only in the United States, Australia, and India, but also across Europe and beyond. A long established and extensive electronic component distribution network has enhanced our global reach and dependability, ensuring cost savings through prompt deliveries worldwide. Client satisfaction is at the heart of our business, where every component counts and every customer matters. Our technical service team is ready to assist you. From product selection to after-sales support, we strive to deliver a seamless and satisfying experience. Are you ready to experience the best in electronic component distribution? Contact X-ON Electronics today and discover why X-On are a preferred choice for the W948D6FBHX6E and other electronic components in the DRAM category and beyond.

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W948D6FB / W948D2FB 256Mb Mobile LPDDR TABLE OF CONTENTS 1. GENERAL DESCRIPTION .................................................................................................. 4 2. FEATURES .......................................................................................................................... 4 3. PIN CONFIGURATION ........................................................................................................ 5 3.1 Ball Assignment: LPDDR x16 ..................................................................................................... 5 3.2 Ball Assignment: LPDDR x32 ..................................................................................................... 5 4. PIN DESCRIPTION ............................................................................................................. 6 4.1 Signal Descriptions ..................................................................................................................... 6 4.2 Addressing Table ........................................................................................................................ 7 5. BLOCK DIAGRAM .............................................................................................................. 8 5.1 Block Diagram ............................................................................................................................ 8 5.2 Simplified State Diagram ............................................................................................................ 9 6. FUNCTION DESCRIPTION ............................................................................................... 10 6.1 Initialization ............................................................................................................................... 10 6.1.1 Initialization Flow Diagram ............................................................................................................. 11 6.1.2 Initialization Waveform Sequence ................................................................................................. 12 6.2 Register Definition .................................................................................................................... 12 6.2.1 Mode Register Set Operation ........................................................................................................ 12 6.2.2 Mode Register Definition ............................................................................................................... 13 6.2.3. Burst Length ................................................................................................................................. 13 6.3 Burst Definition ......................................................................................................................... 14 6.4 Burst Type ................................................................................................................................ 15 6.5 Read Latency ............................................................................................................................ 15 6.6 Extended Mode Register Description ....................................................................................... 15 6.6.1 Extended Mode Register Definition ............................................................................................... 16 6.7 Status Register Read ................................................................................................................ 16 6.7.1 SRR Register (A n:0 = 0) .............................................................................................................. 17 6.7.2 Status Register Read Timing Diagram .......................................................................................... 18 6.8 Partial Array Self Refresh ......................................................................................................... 19 6.9 Automatic Temperature Compensated Self Refresh ................................................................ 19 6.10 Output Drive Strength ............................................................................................................. 19 6.11 Commands ............................................................................................................................. 19 6.11.1 Basic Timing Parameters for Commands .................................................................................... 19 6.11.2 Truth Table - Commands ............................................................................................................. 20 6.11.3 Truth Table - DM Operations ....................................................................................................... 21 6.11.4 Truth Table - CKE ........................................................................................................................ 21 6.11.5 Truth Table - Current State BANKn - Command to BANKn ........................................................ 22 6.11.6 Truth Table - Current State BANKn, Command to BANKn ......................................................... 23 7. OPERATION ...................................................................................................................... 24 7.1. Deselect ................................................................................................................................... 24 7.2. No Operation ........................................................................................................................... 24 7.2.1 NOP Command ............................................................................................................................. 25 7.3 Mode Register Set .................................................................................................................... 25 Publication Release Date : Oct, 15, 2012 - 1 - Revision : A01-004 W948D6FB / W948D2FB 256Mb Mobile LPDDR 7.3.1 Mode Register Set Command ....................................................................................................... 25 7.3.2 Mode Register Set Command Timing ........................................................................................... 26 7.4. Active ....................................................................................................................................... 26 7.4.1 Active Command ........................................................................................................................... 26 7.4.2 Bank Activation Command Cycle .................................................................................................. 27 7.5. Read ........................................................................................................................................ 27 7.5.1 Read Command ............................................................................................................................. 28 7.5.2 Basic Read Timing Parameters ..................................................................................................... 28 7.5.3 Read Burst Showing CAS Latency ................................................................................................ 29 7.5.4 Read to Read ................................................................................................................................. 29 7.5.5 Consecutive Read Bursts .............................................................................................................. 30 7.5.6 Non-Consecutive Read Bursts ...................................................................................................... 30 7.5.7 Random Read Bursts .................................................................................................................... 31 7.5.8 Read Burst Terminate.................................................................................................................... 31 7.5.9 Read to Write ................................................................................................................................. 32 7.5.10 Read to Pre-charge ..................................................................................................................... 32 7.6 Write ......................................................................................................................................... 33 7.6.1 Write Command ............................................................................................................................. 34 7.6.2 Basic Write Timing Parameters ..................................................................................................... 34 7.6.3 Write Burst (min. and max. tDQSS) ............................................................................................... 35 7.6.4 Write to Write ................................................................................................................................. 35 7.6.5 Concatenated Write Bursts ............................................................................................................ 36 7.6.6 Non-Consecutive Write Bursts ...................................................................................................... 36 7.6.7 Random Write Cycles .................................................................................................................... 37 7.6.8 Write to Read ................................................................................................................................. 37 7.6.9 Non-Interrupting Write to Read ...................................................................................................... 37 7.6.10 Interrupting Write to Read ........................................................................................................... 38 7.6.11 Write to Precharge ....................................................................................................................... 38 7.6.12 Non-Interrupting Write to Precharge ............................................................................................ 38 7.6.13 Interrupting Write to Precharge ................................................................................................... 39 7.7 Precharge ................................................................................................................................. 39 7.7.1 Precharge Command ..................................................................................................................... 40 7.8 Auto Precharge ......................................................................................................................... 40 7.9 Refresh Requirements .............................................................................................................. 40 7.10 Auto Refresh ........................................................................................................................... 40 7.10.1 Auto Refresh Command .............................................................................................................. 41 7.11 Self Referesh .......................................................................................................................... 41 7.11.1 Self Refresh Command ............................................................................................................... 42 7.11.2 Auto Refresh Cycles Back-to-Back ............................................................................................. 42 7.11.3 Self Refresh Entry and Exit ......................................................................................................... 43 7.12 Power Down ........................................................................................................................... 43 7.12.1 Power-Down Entry and Exit ......................................................................................................... 43 7.13 Deep Power Down .................................................................................................................. 44 7.13.1 Deep Power-Down Entry and Exit ............................................................................................... 44 7.14 Clock Stop .............................................................................................................................. 45 Publication Release Date : Oct, 15, 2012 - 2 - Revision : A01-004

Tariff Desc

8542.32.00 -- Memories
               Monolithic integrated circuits:
WINBOND ELECTRONICS
WINBOND ELECTRONICS CORP AMERICA

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