W957D6HBCX7I TR Winbond

W957D6HB 128Mb Async./Burst/Sync./A/D MUX TABLE OF CONTENTS 1. GENERAL DESCRIPTION .......................................................................................................... 3 2. FEATURES.................................................................................................................................. 3 3. ORDERING INFORMATION ....................................................................................................... 3 4. PIN CONFIGURATION ................................................................................................................ 4 4.1 Ball Assignment ............................................................................................................................... 4 5. PIN DESCRIPTION ..................................................................................................................... 5 5.1 Signal Description ............................................................................................................................ 5 6. BLOCK DIAGRAM ...................................................................................................................... 6 7. INSTRUCTION SET .................................................................................................................... 7 7.1 Bus Operation .................................................................................................................................. 7 8. FUNCTIONAL DESCRIPTION .................................................................................................... 8 8.1 Power Up Initialization ..................................................................................................................... 8 8.1.1 Power-Up Initialization Timing ................................................................................................................... 8 8.2 Bus Operating Modes ...................................................................................................................... 8 8.2.1 Asynchronous Modes ................................................................................................................................ 8 8.2.1.1 READ Operation (ADV LOW) ......................................................................................................................... 9 8.2.1.2 WRITE Operation (ADV LOW) ....................................................................................................................... 9 8.2.2 Burst Mode Operation .............................................................................................................................. 10 8.2.2.1 Burst Mode READ (4-word burst) ................................................................................................................... 10 8.2.2.2 Burst Mode WRITE (4-word burst) ................................................................................................................. 11 8.2.2.3 Refresh Collision During Variable-Latency READ Operation ......................................................................... 12 8.2.3 Mixed-Mode Operation ............................................................................................................................ 13 8.2.4 WAIT Operation ....................................................................................................................................... 13 8.2.4.1 Wired-OR WAIT Configuration ....................................................................................................................... 13 8.2.5 LB / UB Operation ................................................................................................................................. 14 8.3 Low Power Operation .................................................................................................................... 14 8.3.1 Standby Mode Operation ......................................................................................................................... 14 8.3.2 Temperature Compensated Refresh ....................................................................................................... 14 8.3.3 Partial-Array Refresh ............................................................................................................................... 14 8.3.4 Deep Power-Down Operation .................................................................................................................. 14 8.4 Registers ....................................................................................................................................... 15 8.4.1 Access Using CRE .................................................................................................................................. 15 8.4.1.1 Configuration Register WRITE Asynchronous Mode Followed by READ Operation ...................................... 15 8.4.1.2 Configuration Register WRITE Synchronous Mode Followed by READ Operation ........................................ 16 8.4.1.3 Configuration Register READ Asynchronous Mode Followed by READ ARRAY Operation ........................... 17 8.4.1.4 Configuration Register READ Synchronous Mode Followed by READ ARRAY Operation ............................ 18 8.4.2 Software Access ...................................................................................................................................... 19 8.4.2.1 Load Configuration Register ........................................................................................................................... 19 8.4.2.2 Read Configuration Register .......................................................................................................................... 20 8.4.3 Bus Configuration Register ...................................................................................................................... 20 8.4.3.1 Bus Configuration Register Definition ............................................................................................................ 21 8.4.3.2 Burst Length (BCR 2:0 ) Default = Continuous Burst ..................................................................................... 22 8.4.3.3 Burst Wrap (BCR 3 ) Default = No Wrap ........................................................................................................ 22 8.4.3.4 Sequence and Burst Length ........................................................................................................................... 23 8.4.3.5 Drive Strength (BCR 5:4 ) Default = Outputs Use Half-Drive Strength ........................................................... 24 8.4.3.6 Table of Drive Strength ................................................................................................................................... 24 8.4.3.7 WAIT Configuration. (BCR 8 ) ........................................................................................................................ 24 8.4.3.8 WAIT Polarity (BCR 10 ) ................................................................................................................................. 24 8.4.3.9 WAIT Configuration During Burst Operation ................................................................................................... 25 8.4.3.10 Latency Counter (BCR 13:11 ) Default = Three Clock Latency .................................................................... 25 8.4.3.11 Initial Access Latency (BCR 14 ) Default = Variable ..................................................................................... 25 8.4.3.12 Allowed Latency Counter Settings in Variable Latency Mode ....................................................................... 25 Publication Release Date: Aug. 17, 2016 Revision: A01-005 - 1 - W957D6HB 8.4.3.13 Latency Counter (Variable Initial Latency, No Refresh Collision) .................................................................. 26 8.4.3.14 Allowed Latency Counter Settings in Fixed Latency Mode ........................................................................... 26 8.4.3.15 Latency Counter (Fixed Latency) ................................................................................................................. 27 8.4.3.16 Operating Mode (BCR 15 ) ........................................................................................................................... 27 8.4.4 Refresh Configuration Register ............................................................................................................... 28 8.4.4.1 Refresh Configuration Register Mapping ....................................................................................................... 28 8.4.4.2 Partial Array Refresh (RCR 2:0 ) Default = Full Array Refresh ....................................................................... 28 8.4.4.3 Address Patterns for PAR (RCR 4 = 1)......................................................................................................... 29 8.4.4.4 Deep Power-Down (RCR 4 ) Default = DPD Disabled ................................................................................... 29 8.4.5 Device Identification Register .................................................................................................................. 29 8.4.5.1 Device Identification Register Mapping .......................................................................................................... 29 9. ELECTRICAL CHARACTERISTIC ........................................................................................... 30 9.1 Absolute Maximum DC, AC Ratings .............................................................................................. 30 9.2 Electrical Characteristics and Operating Conditions ....................................................................... 30 9.3 Deep Power-Down Specifications .................................................................................................. 31 9.4 Partial Array Self Refresh Standby Current .................................................................................... 31 9.5 Capacitance ................................................................................................................................... 31 9.6 AC Input-Output Reference Wave form .......................................................................................... 31 9.7 AC Output Load Circuit .................................................................................................................. 31 10. TIMING REQUIRMENTS ......................................................................................................... 32 10.1 Read, Write Timing Requirements ............................................................................................... 32 10.1.1 Asynchronous READ Cycle Timing Requirements ............................................................................... 32 10.1.2 Burst READ Cycle Timing Requirements .............................................................................................. 33 10.1.3 Asynchronous WRITE Cycle Timing Requirements .............................................................................. 34 10.1.4 Burst WRITE Cycle Timing Requirements ............................................................................................ 35 10.2 TIMING DIAGRAMS .................................................................................................................... 36 10.2.1 Initialization Period ................................................................................................................................. 36 10.2.2 DPD Entry and Exit Timing Parameters ................................................................................................ 36 10.2.3 Initialization and DPD Timing Parameters ............................................................................................. 36 10.2.4 Asynchronous READ ............................................................................................................................. 37 10.2.5 Single Access Burst READ Operation - Variable Latency..................................................................... 38 10.2.6 Four Word Burst READ Operation-Variable Latency ............................................................................ 39 10.2.7 Single-Access Burst READ Operation-Fixed Latency ........................................................................... 40 10.2.8 Four Word Burst READ Operation-Fixed Latency ................................................................................. 41 10.2.9 Burst READ Terminate at End-of-Row (Wrap Off) ................................................................................ 42 10.2.10 Burst READ Row Boundary Crossing ................................................................................................. 43 10.2.11 Asynchronous WRITE ......................................................................................................................... 44 10.2.12 Burst WRITE Operation Variable Latency Mode .............................................................................. 45 10.2.13 Burst WRITE Operation-Fixed Latency Mode ..................................................................................... 46 10.2.14 Burst WRITE Terminate at End of Row (Wrap Off) ............................................................................. 47 10.2.15 Burst WRITE Row Boundary Crossing ................................................................................................ 48 10.2.17 Asynchronous WRITE Followed by Burst READ ................................................................................ 50 10.2.18 Burst READ Followed by Asynchronous WRITE ................................................................................ 51 10.2.19 Asynchronous WRITE Followed by Asynchronous READ .................................................................. 52 11. PACKAGE DESCRIPTION ..................................................................................................... 53 11.1 Package Dimension ..................................................................................................................... 53 12. REVISION HISTORY ............................................................................................................... 54 Publication Release Date: Aug. 17, 2016 Revision: A01-005 - 2 -