W957D8MFYA5I TR Winbond

W957D8MFYA / W957A8MFYA 128Mb HyperRAM Table of Contents- 1. FEATURES .................................................................................................................................................................................. 3 2. ORDER INFORMATION .............................................................................................................................................................. 3 3. BALL ASSIGNMENT.................................................................................................................................................................... 4 4. BALL DESCRIPTIONS ................................................................................................................................................................ 5 5. BLOCK DIAGRAM ....................................................................................................................................................................... 6 5.1 Function Block Diagram (Single Die) ............................................................................................................................. 6 5.2 Package Block Diagram (DDP) ...................................................................................................................................... 7 6. FUNCTIONAL DESCRIPTION ..................................................................................................................................................... 8 6.1 HyperBus Interface ........................................................................................................................................................ 8 7. HYPERBUS TRANSACTION DETAILS ..................................................................................................................................... 11 7.1 Command/Address Bit Assignments ............................................................................................................................ 11 7.2 Read Transactions ....................................................................................................................................................... 14 7.3 Write Transactions (Memory Array Write) .................................................................................................................... 15 7.4 Write Transactions without Initial Latency (Register Write) .......................................................................................... 16 8. MEMORY SPACE ...................................................................................................................................................................... 17 8.1 HyperBus Interface Memory Space addressing ........................................................................................................... 17 8.1.1 Density and Row Boundaries ......................................................................................................................... 17 9. REGISTER SPACE ................................................................................................................................................................... 18 9.1 HyperBus Interface Register Addressing ..................................................................................................................... 18 9.2 Register Space Access ................................................................................................................................................ 19 9.3 Device Identification Registers ..................................................................................................................................... 20 9.4 Configuration Register 0 .............................................................................................................................................. 20 9.4.1 Wrapped Burst ............................................................................................................................................... 21 9.4.2 Hybrid Burst ................................................................................................................................................... 22 9.4.3 Initial Latency ................................................................................................................................................. 23 9.4.4 Fixed Latency ................................................................................................................................................ 23 9.4.5 Drive Strength ................................................................................................................................................ 23 9.4.6 Deep Power Down ......................................................................................................................................... 23 9.5 Configuration Register 1 .............................................................................................................................................. 24 9.5.1 Master Clock Type ......................................................................................................................................... 24 9.5.2 Partial Array Refresh ...................................................................................................................................... 24 9.5.3 Hybrid Sleep .................................................................................................................................................. 25 9.5.4 Distributed Refresh Interval ........................................................................................................................... 25 9.6 Dual-Die-Package (DDP) Application .......................................................................................................................... 26 9.6.1 Die Stack Addressing ..................................................................................................................................... 26 9.6.2 Burst Operations - Die Boundary Crossing .................................................................................................... 26 9.6.3 Die number assignment ................................................................................................................................. 26 9.6.4 Latency mode ................................................................................................................................................ 26 9.6.5 IO pad capacitance ........................................................................................................................................ 26 9.6.6 Current consumption ...................................................................................................................................... 27 9.6.7 Partial Refresh ............................................................................................................................................... 27 9.6.8 Hybrid Sleep Mode (HSM) and Deep Power Down (DPD) mode................................................................... 27 10. INTERFACE STATES ................................................................................................................................................................ 28 The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Publication Release Date: Sep. 03, 2020 Revision: A01-001 - 1 - W957D8MFYA / W957A8MFYA 10.1 IO condition of interface states..................................................................................................................................... 28 10.2 Power Conservation Modes ......................................................................................................................................... 29 10.2.1 Interface Standby ........................................................................................................................................... 29 10.2.2 Active Clock Stop ........................................................................................................................................... 29 10.2.3 Hybrid Sleep .................................................................................................................................................. 29 10.2.4 Deep Power Down ......................................................................................................................................... 30 11. ELECTRICAL SPECIFICATIONS .............................................................................................................................................. 31 11.1 Absolute Maximum Ratings ......................................................................................................................................... 31 11.2 Latch up Characteristics .............................................................................................................................................. 31 11.3 Operating Ranges ........................................................................................................................................................ 31 11.3.1 DC Characteristics ......................................................................................................................................... 31 11.3.2 Operating Temperature .................................................................................................................................. 31 11.3.3 ICC Characteristics ........................................................................................................................................ 32 11.3.4 Power-Up Initialization ................................................................................................................................... 33 11.3.5 Power-Down .................................................................................................................................................. 34 11.3.6 Hardware Reset ............................................................................................................................................. 35 11.3.7 Capacitance Characteristics .......................................................................................................................... 36 11.4 Input Signal Overshoot ................................................................................................................................................ 36 12. TIMING SPECIFICATIONS ........................................................................................................................................................ 37 12.1 Key to Switching Waveforms ....................................................................................................................................... 37 12.2 AC Test Conditions ...................................................................................................................................................... 37 12.3 Timing Reference Levels for t and t ......................................................................................................................... 38 IS IH 12.4 AC Characteristics ....................................................................................................................................................... 39 12.4.1 Read Transactions ......................................................................................................................................... 39 12.4.2 Write Transactions ......................................................................................................................................... 43 12.4.3 Hybrid Sleep Timings ..................................................................................................................................... 45 12.4.4 Deep Power down Timings ............................................................................................................................ 45 13. PACKAGE SPECIFICATION ..................................................................................................................................................... 46 14. REVISION HISTORY ................................................................................................................................................................. 47 The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Publication Release Date: Sep. 03, 2020 Revision: A01-001 - 2 -