VCU110 Evaluation Board User Guide UG1073 (v1.5) April 19, 2019Revision History The following table shows the revision history for this document. Date Version Revision 04/19/2019 1.5 Added Electrostatic Discharge Caution. Updated component information in QDR2+ Component Memory and RLD3 Component Memory. Removed the constraints file in Appendix D, Xilinx Design Constraints and added instructions to access the file. Updated Appendix G, Regulatory and Compliance Information. 07/28/2017 1.4 Updated the UltraScale XCVU190-2FLGC2104EES9847 FPGA part number to XCVU190-2FLGC2104E throughout. Standardized figure format. Added Documentation Navigator and Design Hubs. 03/15/2017 1.3 Updated Micron HMC part number throughout. Updated Table 1-16, Table 1-18, Table 1-51, and Table 1-52. 03/26/2016 1.2 Updated Dual Quad-SPI Flash Memory, Micro-SD Card Interface, and FMC HPC1 Connector J2. Updated Table 1-15, Table 1-16, Table 1-17, Table 1-18, Table 1-19, Table 1-20, Table 1-23, Table 1-24, Table 1-25, Table 1-40, and Table 1-59. Added thickness information to Appendix F, Board Specifications. 01/16/2016 1.1 Updated the UltraScale XCVU190-2FLGC2104EES9847 FPGA part number throughout. 11/21/2015 1.0 Initial Xilinx release. VCU110 Evaluation Board 2 Send Feedback UG1073 (v1.5) April 19, 2019 www.xilinx.com