100G IEEE 802.3bj Reed-Solomon FEC v2.0 PB028 April 4, 2018 LogiCORE IP Product Brief LogiCORE IP Facts Table Introduction Core Specifics The Xilinx LogiCORE IP IEEE 802.3bj Supported UltraScale+ (1) Reed-Solomon Forward Error Correction Device Family Virtex UltraScale (RS-FEC) core implements the RS-FEC sublayer Supported User AXI4-Lite, Configuration and Status bus Interfaces as described in IEEE 802.3bj-2014, section 91. Provided with Core Design Files Encrypted RTL Additional Documentation Example Design Verilog A product guide is available for this core. Test Bench Not Provided Access to this material may be requested by Constraints File Xilinx Constraints File clicking on this registration link: Simulation Encrypted Verilog www.xilinx.com/member/ieee802-3bj-rs-fec/ Model index.htm Supported N/A S/W Driver (2) Tested Design Flows Features Design Entry Vivado Design Suite IEEE 802.3bj-2014 TX and RX For supported simulators, see the Simulation Xilinx Design Tools: Release Notes Guide. Low latency design Synthesis Vivado Design Suite Supports 100 Gb/s Support Provided by Xilinx www.xilinx.com/support Supports RS(528,514) KR4 and RS(544,514) Notes: KP4 1. For a complete list of supported devices, see the Vivado IP Configuration and status bus catalog. 2. For the supported versions of the tools, see the Selectable AXI4-Lite interface for status Xilinx Design Tools: Release Notes Guide. output Transcode Bypass mode for direct access to RS-FEC encoder/decoder CAUI-4 support in Active mode CAUI-4 and CAUI-10 support in Bypass mode (KR4 mode only) Example reference design demonstrating integrated 100G Ethernet IP with RS-FEC ECC RAM option Status outputs for monitoring the core and for statistics generation Copyright 20152018 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. AMBA, AMBA Designer, ARM, ARM1176JZ-S, CoreSight, Cortex, and PrimeCell are trademarks of ARM in the EU and other countries. All other trademarks are the property of their respective owners. 100G IEEE802.3bj RS-FEC v2.0 1 Send Feedback PB028 April 4, 2018 www.xilinx.comProduct Brief Overview The 100G IEEE 802.3bj RS-FEC core implements the OSI layer, RS-FEC, shown shaded in Figure 1. X-Ref Target - Figure 1 LAN CSMA/CD Layers Higher Layers OSI Reference LLC-Logical Link Control Model Layers MAC Control (Optional) Application MAC - Media Access Control Presentation Reconciliation Session CGMII Transport 100GBASE-R PCS RS-FEC Network PMA Data Link PMD AN Physical Medium PCS - Physical Coding Sublayer CGMII 100 Gigabit Media Independent Interface PMA - Physical Medium Attachment PMD - Physical Medium Dependent X14449 Figure 1: IEEE Std 802.3-2014 Ethernet Model The RS-FEC layer of IEEE Std 802.3bj-2014 defines more than just the RS encoder/decoder. It defines several stages of synchronization, alignment, and reordering which are necessary for the layer to communicate with preceding and subsequent layers. The IEEE 802.3-2014 block diagram is shown in Figure 2. 100G IEEE802.3bj RS-FEC v2.0 2 Send Feedback PB028 April 4, 2018 www.xilinx.com