EF-DI-25G-RS-FEC-PROJ Xilinx

Multi-Channel 25G Reed-Solomon Forward Error Correction PB057 (v1.0) December 5, 2018 LogiCORE IP Product Brief Introduction The Multi-Channel 25G Reed-Solomon Forward Error Correction implements the Reed-Solomon Forward Error Correction (RS-FEC) sublayer for one to four 25G Ethernet channels, making use of the hard 100G RS-FEC IP block in the Xilinx UltraScale+ devices. Xilinx also provides a soft 25G IEEE 802.3by Reed-Solomon Forward Error Correction IP core. The Multi-Channel 25G RS-FEC is intended for applications where two or more channels are required, a CMAC hard block is available, and there is a need to reduce the amount of logic resources. It is possible to use a combination of the IP cores, for example by using the Multi- Channel 25G RS-FEC core to implement the receive paths and the 25G IEEE 802.3by Reed- Solomon Forward Error Correction soft core for the transmit paths. Features Support for between 1 and 4 parallel 25GE channels using hard RS-FEC function in UltraScale+ CMAC block Conform to IEEE Std 802.3by and 25/50G Gigabit Ethernet Consortium Schedule 3 (v1.6) ( Multi-Channel 25G Reed-Solomon Forward Error Correction IP Facts LogiCORE IP Facts Table Core Specifics 1 Supported Device Family Virtex UltraScale+ Kintex UltraScale+ Zynq UltraScale+ MPSoC Zynq UltraScale+ RFSoC Supported User Interfaces Configuration and status bus Resources Performance and Resource Use web page Provided with Core Design Files Encrypted RTL Example Design Verilog (Simulation-Only) Test Bench Not Provided Constraints File Xilinx Constraints File Simulation Model Encrypted Verilog Supported S/W Driver N/A 2 Tested Design Flows Design Entry Vivado Design Suite Simulation For supported simulators, see the Xilinx Design Tools: Release Notes Guide. Synthesis Vivado Design Suite Support Provided by Xilinx at the Xilinx Support web page Notes: 1. For a complete list of supported devices, see the Vivado IP catalog. 2. For the supported versions of the tools, see the Xilinx Design Tools: Release Notes Guide. Overview The Multi-Channel 25G RS-FEC core implements up to four instances of the RS-FEC layer which forms part of the IEEE 802.3 25G Ethernet PHY. The RS-FEC layer is shaded in the following figure. PB057 (v1.0) December 5, 2018 www.xilinx.com Send Feedback Multi-Channel 25G Reed-Solomon Forward Error Correction 2