LogiCORE IP Peak Cancellation - Crest Factor Reduction v6.2 PB008 (v6.2) December 5, 2018 LogiCORE IP Product Brief LogiCORE IP Facts Table Introduction Core Specifics The Xilinx LogiCORE IP Peak Cancellation - UltraScale+ Families Crest Factor Reduction (PC-CFR) core is used to Supported UltraScale Architecture (1) Device Family Zynq-7000 SoC limit the dynamic range of the signals being 7Series transmitted in wireless communications and Supported User AXI4-Stream, AXI4-Lite other applications. Interfaces Provided with Core Additional Documentation Design Files Encrypted RTL Example Design Not Provided A product guide is available for this core. To Test Bench VHDL request access to this material, click this Constraints File Vivado XDC registration link: www.xilinx.com/member/ Simulation VHDL and Verilog Structural Simulation Model pc cfr eval/index.htm. Model MATLAB Model available Supported N/A S/W Driver Features (2) Tested Design Flows Design Entry Vivado Design Suite Support for multiple air interface standards. For supported simulators, see the Simulation Xilinx Design Tools: Release Notes Guide. Smart Peak Processing mode for Synthesis Vivado Synthesis supporting wide transmit bandwidth up to 400 MHz, processes incoming samples at Support >1.2 times instantaneous Bandwidth (iBW) Provided by Xilinx www.xilinx.com/support reducing resource utilization. Notes: User selectable carrier configuration 1. For a complete listing of supported devices, see the Vivado IP catalog. agnostic Window Crest Factor Reduction 2. For the supported versions of the tools, see the (WCFR) available as a standalone or a post Xilinx Design Tools: Release Notes Guide. processing stage. Support for power and frequency dynamics. Support for dynamic computation of Cancellation Pulse (CP). Support for optional hard clipper in post processing stage. Meets performance requirements (EVM, PAPR and ACLR) of all air interfaces. For additional features see Features (cont.) Copyright 2011-2018 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. PC-CFR v6.2 1 Send Feedback PB008 December 5, 2018 www.xilinx.comProduct Brief Features (cont.) Configurable clock-to-sample ratio of 1, 2, 3, 4 and 8. Configurable number of Cancellation Pulse Generators (CPGs) of 1 to 12 per iteration. Support for 1, 2, 4, 8, and 16 antennas. Support for 1 to 8 iterations. Quantization support for 16 and 18 bits. Support for cancellation pulse read back in static mode and base pulse read back in dynamic mode. Support for read back of CFR configuration and statistics registers. Support to work as a Stand-alone Hard Clipper. Optional feature to operate WCFR without smart peak processing. Support for data-path delay matched TUSER forwarding feature. A maximum of five different RATs are supported. The total number of carriers using all RATs is thirty. LTE 5 Mhz and LTE 10 Mhz are considered as different RATs because the corresponding base pulses are different. Overview Crest Factor Reduction (CFR) is used to limit the dynamic range of the signals being transmitted in wireless communications and other applications. Multi-user and multi-carrier signals often have a high peak-to-average ratio (PAR). This places high demands on the data converters and especially limits the efficiency of operation of the Power Amplifiers (PAs) used in cellular base stations. Reducing the PAR is therefore beneficial in increasing PA efficiency by allowing higher average power to be transmitted before saturation occurs. In a modern transmit chain, CFR is often incorporated with Digital Pre-distortion (DPD), which acts to linearize the PA, allowing operation at maximum efficiency with spectral compliance. CFR complements DPD because it levels the signal peaks, making accurate correction estimation easier. The Xilinx PC-CFR core is an efficient, flexible and easy-to-use implementation that supports 7 series, Zynq-7000, and UltraScale FPGAs. It is configurable both in function, supporting all major cellular wireless air interfaces, and in use, supporting many clocking and resource requirements. It can also handle dynamic power and frequency variations in the incoming data by computing the cancellation pulse coefficients dynamically. PC-CFR v6.2 2 Send Feedback PB008 December 5, 2018 www.xilinx.com