LogiCORE IP Endpoint PIPE v1.8 for PCI Express DS321 July 23, 2010 Product Specification Introduction LogiCORE IP Facts Table The LogiCORE IP Endpoint PIPE (PHY Interface) for Core Specifics PCI Express 1-lane core is a high-bandwidth scalable Supported (2) Spartan-3, Spartan-3E, Spartan-3A (1) Device Family and reliable serial interconnect intellectual property XC3S1000-4 Spartan-3 building block for use with the Spartan-3, Spartan-3E, Minimum and Spartan-3A FPGAs in conjunction with an external Device Spartan-3E XC3S500E-4 Requirement PHY device. This solution, compliant with the PCI Spartan-3A XC3S700A-4 Express Base Specification v1.1, is a flexible low-cost (3) Resources chipset that can be used in a wide variety of Block Configuration LUTs FFs (4) RAMs high-volume applications including add-in cards, host bus adapters, and high-end server and graphics cards. 1-Lane 5880- 4650- 8 (5) (5) 6150 4790 Endpoint PIPE PCI Express offers a serial architecture that alleviates Supported PHY NXP PX1011B-EL1 some of the limitations of parallel bus architectures by Provided with Core using clock data recovery (CDR) and differential Product Specification signaling. Using CDR (as opposed to source Getting Started Guide Documentation synchronous clocking) lowers pin count, enables User Guide Instantiation Template superior frequency scalability, and makes data synchronization easier. The layered architecture of PCI Design Files Netlist Express provides for future attachment to copper, Example Design Verilog optical, or emerging physical signaling media. PCI Test Bench Verilog Express technology, adopted by the PCI-SIG as the next Constraints File Specify Xilinx Constraints File generation PCI, is backward-compatible to the existing Simulation Verilog and VHDL PCI software model. Model Tested Design Tools The Xilinx solutions for PCI Express set the industry standard for a high-performance and cost-efficient Mentor Graphics ModelSim PE/SE v6.5c and above third-generation I/O solution by providing higher Design Entry Synopsys VCS and VCS MX 2009.12 and Tools above bandwidth per pin, low overhead, low latency, reduced Cadence Incisive Enterprise Simulator (IES) signal integrity issues, and CDR architecture. v9.2 and above Simulation Version of Simulator Tools Tested Xilinx Endpoint solutions for PCI Express are Synthesis Tools compatible with industry standard application form Synplicity Synplify, Xilinx XST (Verilog only) factors such as PCI Express Card Electromechanical (CEM) Support v1.1 and PCI Industrial Computer Manufacturers Group Provided by Xilinx, Inc. (PICMG) 3.4 specifications. 1. For a complete listing of supported devices, see the release notes for this core. 2. Spartan-3AN is not a supported device family. 3. The precise number of slices depends on the user configuration of the interface and the level of resource sharing with adjacent logic. 4. Based on 18K block RAMs (or 36K - select appropriate size). 5. This range indicates resources used for a 2BAR7BAR implementation. Copyright 2005-2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. PCI, PCI Express, PCIe, and PCI-X are trademarks of PCI-SIG. DS321 July 23, 2010 www.xilinx.com 1 Product SpecificationLogiCORE IP Endpoint PIPE v1.8 for PCI Express Features High-performance, highly flexible, scalable, reliable, and general purpose I/O core Compliant with the PCI Express Base Specification v1.1 Compatible with conventional PCI software model Fully compliant with PCI Express transaction ordering rules Six individually programmable/configurable BARs and expansion ROM BAR Supports MSI and INTX emulation 32-bit internal data path Supports removal of corrupt packets for error detection and recovery Compatible with PCI/PCI Express power management functions Active state power management (ASPM) Programmed power management (PPM) Used in conjunction with NXP PX1011B PCI Express standalone PHY to achieve high transceiver capability 2.5 Gbps line speed Elastic buffers and clock compensation Automatic clock and data recovery 8b/10b encode and decode Offers standardized easy-to-use Xilinx LocalLink interface Packet-based full-duplex communication Back-to-back transactions enable greater link bandwidth utilization Enables flow control of data and discontinuance of an in-process transaction in the transmit direction Enables flow control of data in the receive direction Automatically decodes and removes error forwarding packet indicator from received data Supports a maximum transaction payload of up to 512 bytes Fully configurable using the Xilinx CORE Generator v12.2 Design verified using a Xilinx proprietary test bench Applications The Endpoint PIPE for PCI Express core architecture enables a broad range of computing and consumer communications target applications, emphasizing performance, cost, scalability, feature extensibility and mission-critical reliability. Typical applications include: Test equipment Consumer graphics boards Medical imaging equipment Data communications networks Telecommunications networks Broadband deployments Cross-connects Workstation and mainframe backbones Network interface cards DS321 July 23, 2010 www.xilinx.com 2 Product Specification