Polar Encoder/Decoder v1.0 PB051 February 4, 2021 LogiCORE IP Product Brief LogiCORE IP Facts Table Introduction Core Specifics The Polar Encoder/Decoder soft IP core supports Versal ACAP Supported Polar encoding and decoding. The Polar codes UltraScale, UltraScale+ (1) Device Family are configurable and can be used on a block- 7 Series by-block basis. Supported User AXI4-Lite, AXI4-Stream Interfaces Note: In this document, a block is the general term Provided with Core for an atomic unit of data processed by an encoder Design Files N/A or decoder. A codeword is the specific form of an encoded block and is used when discussing the Example Design IP Integrator Block Diagram code parameters used to generate it. Test Bench N/A Constraints File Xilinx Design Constraints (XDC) System Verilog Secure model Simulation Additional Documentation Bit-accurate C model Model MEX file for use with MATLAB A product guide is available for this core. Supported Standalone S/W Driver Access to this material can be requested by clicking on this registration link: (2) Tested Design Flows www.xilinx.com/member/polar-cores.html Design Entry Vivado Design Suite For supported simulators, see the Simulation (3) Xilinx Design Tools: Release Notes Guide . Synthesis Vivado Features Support Supports 3GPP TS 38.212 V15.1.1 3rd Release Notes Generation Partnership Project Technical and Known Master Answer Record: 70106 Issues Specification Group Radio Access Network All Vivado IP NR Multiplexing and channel coding Master Vivado IP Change Logs: 72775 Change Logs (Release 15) Provided by Xilinx at the Xilinx Support web page (1) Throughput up to: Notes: >80 Mb/s for decoder (N=1024, K=200) 1. For a complete listing of supported devices, see the Vivado IP catalog. >700 Mb/s for encoder (N=1024, K=200) 2. For the supported versions of the tools, see the Xilinx Design Tools: Release Notes Guide. High bandwidth AXI4-Stream interfaces 3. The Early Access version of this core only supports Mentor Graphics Questa Advanced Simulator v10.5c 1. See performance in the Polar Encoder/Decoder Product Guide (PG280). Figures are for a clock frequency of 400 MHz and should be scaled for achieved clock frequency. Throughput is a function of many factors including code size, code mix, clock frequency and augmentation parameters Copyright 20172021 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. AMBA, AMBA Designer, Arm, ARM1176JZ-S, CoreSight, Cortex, PrimeCell, Mali, and MPCore are trademarks of Arm Limited in the EU and other countries. All other trademarks are the property of their respective owners. Polar Encoder/Decoder 1 Send Feedback PB051 February 4, 2021 www.xilinx.comProduct Brief Overview Forward Error Correction (FEC) codes such as Polar codes provide a means to control errors in data transmissions over unreliable or noisy communication channels. The Polar Encoder/Decoder core provides an optimized block for encoding and soft-decision decoding of these codes. Codes can be specified through an AXI4-Lite bus. A block diagram of the Polar Encoder/Decoder core is shown in Figure 1. X-Ref Target - Figure 1 Interfaces On/Off AXI4-Lite Polar Code Description Parameter Bus Polar IP Core 32b AXI4-Lite Slave Parameters Polar Decoder or AXI MM Interface Encoder 32b 32b CTRL STATUS Memory Subsystem O/P 8b 8b DIN WORDS Working O/P Interface I/P DOUT WORDS Memories Buffer Buffer I/P Interface 128b 128b DIN DOUT Up to 16 LLRs per cycle at core clock Key: AXI4-Stream (per sample) AXI4-Stream (per block) AXI4-Lite Internal Memory Bus (arrow shows direction of data flow) X19448-080717 Figure 1: Polar Encoder/Decoder Core Block Diagram Polar Encoder/Decoder 2 Send Feedback PB051 February 4, 2021 www.xilinx.com