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EF-DI-PCIEXP-SITE Xilinx

EF-DI-PCIEXP-SITE electronic component of Xilinx
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Part No.EF-DI-PCIEXP-SITE
Manufacturer: Xilinx
Category: Development Software
Description: Development Software LogiCORE, PCI Express Endpoint, Site License
Datasheet: EF-DI-PCIEXP-SITE Datasheet (PDF)
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



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LogiCORE IP Endpoint v3.7 for PCI Express DS506 April 19, 2010 Product Specification Introduction LogiCORE Facts Core Specifics The LogiCORE Endpoint for PCI Express offers Device (2) (2),(3) Virtex-4 FX , Virtex-5 LX (1) high-bandwidth, scalable, and reliable serial intercon- Families 1-lane 64-bit Endpoint XC4VFX20 -10 nect intellectual property building blocks for use with Minimum 4-lane 64-bit Endpoint XC4VFX20 -10 Virtex-4, and Virtex-5 devices. All cores in the solu- Device 8-lane 64-bit Endpoint XC4VFX60 -11/XC5VLX50T-1 Require- tion (1-lane, 4-lane, and 8-lane) are protocol-compliant 1-lane 32-bit Endpoint XC4VFX20 -10/XC5VLX50T-1 ment and electrically compatible with the PCI Express Base 4-lane 32-bit Endpoint XC4VFX20 -11/XC5VLX50T-1 (4) Endpoint (EP) Product I/O LUT FF Specification v1.1. (5) 1-lane 64-bit Endpoint 1 7800 7000 PCI Express (PCIe) offers a serial architecture that 4-lane 64-bit Endpoint 4 10550 9200 8-lane 64-bit EP Virtex-4 13500 12000 alleviates some of the limitations of parallel bus archi- 8 8-lane 64-bit EP Virtex-5 11400 11200 tectures by using clock data recovery (CDR) and differ- 1-lane 32-bit EP Virtex-4 6300 5100 (5) 1 1-lane 32-bit EP Virtex-5 ential signaling. Using CDR (as opposed to source 5100 4700 4-lane 32-bit EP Virtex-4 8700 7000 synchronous clocking) lowers pin count, enables supe- 4 4-lane 32-bit EP Virtex-5 7200 6700 rior frequency scalability, and makes data synchroniza- (6) Resources CMPS Block Used Tx CMPS tion easier. The layered architecture of PCIe provides RAM Buffers for future attachment to copper, optical, or emerging 1-lane 64-bit Endpoint 12 16 512 physical signaling media. PCIe technology, adopted by 4-lane 64-bit Endpoint 12 16 512 8-lane 64-bit EP Virtex-4 12 PCI-SIG as the next generation PCI, is backward-com- 32 256 8-lane 64-bit EP Virtex-5 6 patible to the existing PCI software model. 1-lane 32-bit EP Virtex-4 8 8 512 1-lane 32-bit EP Virtex-5 4 With higher bandwidth per pin, low overhead, low 4-lane 32-bit EP Virtex-4 12 16 512 latency, reduced signal integrity issues, and CDR archi- 4-lane 32-bit EP Virtex-5 6 (4) Rocket IO Transceivers , tecture, the Xilinx Endpoint solution for PCI Express Special Features Digital Clock Manager, block RAM sets the industry standard for a high-performance, cost- Provided with Core efficient third-generation I/O solution. Product Specification, Getting Started Guide Documentation User Guide, Instantiation Template The Xilinx Endpoint solution for PCIe is compatible Verilog and VHDL Simulation Models Design Files Xilinx Generic Netlist Format (ngo netlist) with industry-standard application form factors such Verilog Example Test Bench & Example Design as the PCI Express Card Electromechanical (CEM) v1.1 Constraints File User Constraints File (UCF) Design Tool Support and the PCI Industrial Computer Manufacturers Group HDL Synthesis Tool Synplicity Synplify, Xilinx XST (PICMG) 3.4 specifications. Implementation Tools Xilinx ISE v12.1 Cadence Incisive Enterprise Simulator (IES) v9.2 The Endpoint solutions for PCIe are defined in the fol- Verification Tools and above, (SWIFT-compliant lowing table. Synopsys VCS and VCS MX 2009.12 and above simulator required) , Mentor Graphics ModelSim v6.5c and above Data Path Support Product FPGA Support Width Provided by Xilinx, Inc. www.xilinx.com/support 1-lane 64-bit Endpoint Virtex-4 FX 64 1. For the complete list of supported devices, see the 12.1 release notes for this core. 4-lane 64-bit Endpoint Virtex-4 FX 64 2. Virtex-4 and Virtex-5 solutions require the latest production silicon stepping and are pending hardware validation. The Xilinx LogiCORE warranty does 8-lane 64-bit Endpoint Virtex-5 LX, Virtex-4 FX 64 not include production usage with engineering sample silicon (ES). 3. XC5VLX50T, XC5VLX110T, and XC5VLX330T are supported. 1-lane 32-bit Endpoint Virtex-5 LX, Virtex-4 FX 32 4. RocketIOMulti-Gigabit Transceiver (MGT) for Virtex-4, RocketIO GTP Transceiver for Virtex-5. 5. In Virtex-4 and Virtex-5 devices, the 1-lane Endpoint core consumes an en- 4-lane 32-bit Endpoint Virtex-5 LX, Virtex-4 FX 32 tire RocketIO transceiver pair. One RocketIO transceiver tile is used for lane 0 the other is unused and tied off inside the core. 6. CMPS: Capability Maximum Payload Size. 20022010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. PCI, PCI Express, PCIe, and PCI-X are trademarks of PCI-SIG. DS506 April 19, 2010 www.xilinx.com 1 Product Specification LogiCORE IP Endpoint v3.7 for PCI Express Features High-performance, highly flexible, scalable, and reliable, general purpose I/O solution Compliant with the PCI Express Base Specification v1.1 Compatible with conventional PCI software model Incorporates Xilinx Smart-IP technology to guarantee critical timing Uses embedded RocketIO transceivers to achieve high-transceiver capability 2.5 Gbps line speed Supports 1-lane, 4-lane, and 8-lane operation Elastic buffers and clock compensation Automatic clock data recovery 8B/10B encode and decode Offers standardized user interface Easy-to-use packet-based protocol Full-duplex communication Back-to-back transactions enable greater link bandwidth utilization Supports flow control of data and discontinuation of an in-process transaction in transmit direction Supports flow control of data in receive direction Support for automatic handling of error forwarded packets Supports removal of corrupted packets for error detection and recovery Compliant with PCI/PCI-Express power management functions Supports a maximum transaction payload of up to 512 bytes Bandwidth scalability with frequency and/or interconnect width Fully compliant with PCI Express transaction ordering rules Design verified using a Xilinx proprietary test bench Applications The Endpoint for PCI Express core architecture enables a broad range of computing and communica- tions target applications, emphasizing performance, cost, scalability, feature extensibility and mission- critical reliability. Typical applications include Data communications networks Telecommunications networks Broadband wired and wireless applications Cross-connects Network interface cards Chip-to-chip and backplane interconnect Crossbar switches Wireless base stations 2 www.xilinx.com DS506 April 19, 2010 Product Specification

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