LTE Uplink Channel Decoder v4.0 PB005 October 5, 2016 LogiCORE IP Product Brief LogiCORE IP Facts Introduction Core Specifics The Xilinx LogiCORE IP LTE Uplink Channel UltraScale+ Decoder implements an AXI4 compliant, UltraScale Supported (1) high-performance, optimized decoder block for Device Family Zynq-7000 All Programmable SoC the 3GPP TS 36.212 v9.3.0 Uplink Shared 7 Series Channel (UL-SCH). Supported User AXI4, AXI4-Stream Interfaces Provided with Core Additional Documentation Design Files Encrypted VHDL Example Design Not provided A full product guide is available for this core. Test Bench VHDL Access to this material can be requested by Constraints File Not provided clicking on this registration link: www.xilinx.com/member/lte ul channel dec eval/ Simulation Encrypted VHDL Model C model and MATLAB model index.htm. (2) Tested Design Tools Design Entry Vivado Design Suite Features Tools For supported simulators, see the Simulation AXI4 compliant interfaces Xilinx Design Tools: Release Notes Guide. Synthesis Tools Vivado Synthesis Uplink Shared Channel decoder for 3GPP TS 36.212 v9.3.0 Support Transport Block Decoder and Channel Provided by Xilinx at the Xilinx Support web page Quality Information Decoder Notes: sub-components can be generated as 1. For the complete list of supported devices, see the Vivado IP stand-alone cores catalog. 2. For the supported versions of the tools, see the TDD/FDD compliant Xilinx Design Tools: Release Notes Guide. Support for on or off chip codeword buffering Integrated descrambling Integrated LLR calculation Fully decoupled decoding chains Fully optimized for speed and area Fully synchronous design using a single clock Bit accurate C model Customer demonstration test bench Copyright 20112016 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. AMBA, AMBA Designer, ARM, ARM1176JZ-S, CoreSight, Cortex, and PrimeCell are trademarks of ARM in the EU and other countries. All other trademarks are the property of their respective owners. LTE Uplink Channel Decoder v4.0 www.xilinx.com 1 Send Feedback PB005 October 5, 2016Functional Description Functional Description The LTE UL Channel Decoder core provides a decoder solution for the 3GPP 36.212 uplink shared channel. The architecture has been designed to provide efficient use of the FPGA resources while also offering a streaming interface to reduce system-level overhead. Technical Support Xilinx provides technical support at the Xilinx Support web page for this LogiCORE IP product when used as described in the product documentation. Xilinx cannot guarantee timing, functionality, or support if you do any of the following: Implement the solution in devices that are not defined in the documentation. Customize the solution beyond that allowed in the product documentation. Change any section of the design labeled DO NOT MODIFY. To contact Xilinx Technical Support, navigate to the Xilinx Support web page. Licensing and Ordering Information This Xilinx LogiCORE IP module is provided under the terms of the Xilinx Turbo Code LogiCORE IP License Terms.The module is shipped as part of the Vivado Design Suite. For full access to all core functionalities in simulation and in hardware, you must purchase a license for the core. Contact your local Xilinx sales representative for information about pricing and availability. For more information, visit the LTE UL Channel Decoder product web page. Information about other Xilinx LogiCORE IP modules is available at the Xilinx Intellectual Property page. For information on pricing and availability of other Xilinx LogiCORE IP modules and tools, contact your local Xilinx sales representative. Disclaimer: France Telecom, for itself and certain other parties, claims certain intellectual property rights covering Turbo Codes technology, and has decided to license these rights under a licensing program called the Turbo Codes Licensing Program. Supply of this IP core does not convey a license nor imply any right to use any Turbo Codes patents owned by France Telecom, TDF or GET. Contact France Telecom for information about its Turbo Codes Licensing Program at the following address: France Telecom R&D, VAT/TURBOCODES, 38, rue du Gnral Leclerc, 92794 Issy Moulineaux, Cedex 9, France. LTE Uplink Channel Decoder v4.0 www.xilinx.com 2 Send Feedback PB005 October 5, 2016