CPRI v8.8 PB012 October 4, 2017 LogiCORE IP Product Brief LogiCORE IP Facts Introduction Core Specifics The LogiCORE IP Common Public Radio (2) UltraScale+ Supported Interface (CPRI) core is a high-performance, (1) UltraScale Device Family (2) low-cost flexible solution for implementation of Zynq-7000 All Programmable SoC (3) 7 Series the CPRI interface. It uses state-of-the-art Supported User Generic data, status, configuration and transceivers to implement the Physical Layer. A Interfaces management interfaces, compact and customizable Data Link Layer is AXI4-Lite management interface implemented in the FPGA logic. Provided with Core Design Files Encrypted register transfer level (RTL) Additional Documentation Example Design VHDL A product guide is available for this core. Test Bench VHDL Access to this material can be requested by Constraints File Xilinx Design Constraints (XDC) going to the CPRI Documentation Lounge. Simulation VHDL, Verilog Models Supported S/W Features N/A Drivers (4) UltraScale architecture-based device Tested Design Flows designs operate at line rates of 614.4, Design Entry Vivado Design Suite 1,228.8, 2,457.6, 3,072, 4,915.2, 6,144, For supported simulators, see the Simulation 8,110.08, 9,830.4, 10,137.6, 12,165.12, and Xilinx Design Tools: Release Notes Guide. 24,330.24 Mb/s using GTHE3, GTYE3, GTHE4 Synthesis Vivado Synthesis or GTYE4 transceivers. 24,330.24 Mb/s line Support rate with optional RS-FEC supported using Provided by Xilinx at the Xilinx Support web page GTYE3 or GTYE4 transceivers, or optional 100G Ethernet RS-FEC using GTYE4 Notes: 1. For a complete list of supported devices, see the Vivado IP transceivers on selected UltraScale+ parts. catalog. 2. Excludes Zynq-7000 007, 010, 014 and 020 devices. Zynq-7000, Virtex-7, and Kintex-7 Excludes Zynq UltraScale+ devices 2cg, 2eg, 3cg and 3eg. device designs operate at line rates of 3. Excludes the Artix-7 100T device in CSG324, FTG256 and CS 614.4, 1,228.8, 2,457.6, 3,072, 4,915.2, 6,144, 324 packages. Excludes Spartan-7 devices 9,830.4, 10,137.6, and 12,165.12 Mb/s using 4. For the supported version of the tool, see the GTXE2, GTHE2 transceivers. Xilinx Design Tools: Release Notes Guide. Artix-7 devices designs operate at line rates of 614.4, 1,228.86 2,457.6, 3,072, 4,915.2, and 6,144 Mb/s using GTPE2 transceivers. Copyright 20122017 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. CPRI is a trademark of Siemens AG. AMBA, AMBA Designer, ARM, ARM1176JZ-S, CoreSight, Cortex, and PrimeCell are trademarks of ARM in the EU and other countries. All other trademarks are the property of their respective owners. CPRI v8.8 1 Send Feedback PB012 October 4, 2017 www.xilinx.comProduct Brief Features (continued) Automatic speed negotiation Supports both Fast (Ethernet) and Slow High-Level Data Link Control (HDLC) Control and Management (C&M) channels per the CPRI Specification v7.0 Ref 1 . Can be configured as a master or slave at generation time. Master core can be switched to operate as a slave through a configuration port. Suitable for use in both Radio Equipment Controllers (RECs) and Radio Equipment (RE), including multi-hop systems. Easy-to-use interface for in-phase (I) and quadrature-phase (Q) data and synchronization together with optional modules for UMTS terrestrial radio access - frequency division duplexing (UTRA-FDD) and Evolved UMTS Terrestrial Radio Access (E-UTRA) data mappings. Supports vendor specific data transport including support for the passing of control AxC information in global system for mobile communications (GSM) systems Delay measurement capability meets CPRI Requirement 21 per CPRI Specification v7.0 Ref 1 Includes the necessary clocking and transceiver logic to enable easy integration into your design Synthesizable example design and simple demonstration test bench provided Optional Reed-Solomon Forward error correction (RS-FEC) supported at 8,110.08, 10,137.6, 12,165.12 and 24,330.24 Mb/s line rates Optional 100G Ethernet RS-FEC supported at a fixed 24,330.24 Mb/s line rate on selected UltraScale+ devices using GTYE4 transceivers CPRI core can be converted into a four lane Receiver Hard FEC IP running at a fixed 24,330.24 Mb/s line rate, on UltraScale+ devices with 100G Ethernet RS-FEC support UTRA-FDD in-phase and quadrature-phase data (I/Q) module supporting 1 to 48 Antenna-Carriers per core Overview The CPRI core implements Layer 1 and Layer 2 of the CPRI specification in UltraScale architecture-based, Zynq-7000, Virtex-7, Kintex-7, and Artix-7 devices. The CPRI core provides these client-side interfaces. I/Q Interface. Consists of a stream of radio data (I/Q samples) that is synchronized to the Universal Mobile Telecommunications System (UMTS) radio frame pulse. Synchronization Interface. Provides the means for the client logic to synchronize to the network time by transmitting the UMTS radio frame pulse and clock frequency. High-Level Data Link Control (HDLC) Interface. Transports management information between master and slave. The HDLC interface is serialized and synchronous. CPRI v8.8 2 Send Feedback PB012 October 4, 2017 www.xilinx.com