LogiCORE IP 3GPP Mixed Mode Turbo Decoder v2.0 PB009 (v2.0) February 4, 2021 LogiCORE IP Product Brief Introduction LogiCORE IP Facts Table The LogiCORE IP 3GPP Mixed Mode Turbo Core Specifics Decoder provides a flexible turbo convolutional Versal ACAP decode function for both LTE and WCDMA air UltraScale+ Families Supported interfaces. The implementation is compliant UltraScale Architecture (1) Device Family Zynq-7000 SoC with the requirements set out in both Ref 1 7 Series and Ref 2 . The core provides an optimized Supported User turbo decode function for base stations at all AXI4-Stream Interfaces form factors, from femto to macrocells. The Provided with Core decoder, when used with a TCC encoder, provides an effective way of transmitting data Design Files Encypted RTL reliably over noisy data channels. Example Design VHDL Test Bench VHDL Additional Documentation Constraints File Not Provided A full product guide is available for this core. Simulation Encrypted VHDL Model C Model and MATLAB Model Access to this material can be requested by clicking on this registration link: Supported N/A S/W Driver www.xilinx.com/member/mm tcc dec eval/index.htm (2) Tested Design Flows Features Design Entry Vivado Design Suite Three versions of this core can be For supported simulators, see the Simulation Xilinx Design Tools: Release Notes Guide. generated, each supporting different Synthesis Vivado Synthesis standard options: Support LTE only Release Notes UMTS only and Known Master Answer Record: 54471 Issues LTE and UMTS All Vivado IP Master Vivado IP Change Logs: 72775 Change Logs When UMTS and LTE are both supported Provided by Xilinx at the Xilinx Support web page the core can switch between different standards on a block by block basis. Notes: 1. For a complete listing of supported devices, see the Vivado IP Each core is completely self contained, catalog. 2. For the supported versions of the tools, see the requiring nothing else to decode data. Xilinx Design Tools: Release Notes Guide. All 3GPP LTE block sizes supported: 188 different block sizes in the range 406144 All 3GPP UMTS block sizes supported, that is block sizes in the range 40-5114. See Feature Summary for additional features. Copyright 2018-2021 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. 3GPP Mixed Mode Turbo Decoder v2.0 1 Send Feedback PB009 (v2.0) February 4, 2021 www.xilinx.comProduct Brief Feature Summary Configurable with either 1, 2, 4 or 8 decode units, allowing resource utilization to be optimized while meeting system performance requirements at all base station form factors. Dynamically selectable number of iterations 1-15. Support for MAX, MAX SCALE and MAX STAR algorithms. AXI4-Stream interfaces used for control and data input/output. C model and MATLAB MEX function available for bit accurate modelling of error correcting performance. Number representation: Twos complement fractional. Data Input: 7 or 8 bits (4 or 5 integer bits with 3 fractional bits) Hardware DSP units can be used instead of logic resources to tailor the core resource usage to specific user applications. Demonstration test bench to show an example of core usage. Integrated scheduler ensures that decode latency remains virtually constant with variable block sizes. Overview The TCC decoder is used in conjunction with a TCC encoder to provide an effective way of transmitting data reliably over noisy data channels. The turbo decoder operates very well under low signal-to-noise conditions and provides a performance close to the theoretical optimal performance defined by the Shannon limit Ref 3 . References 1. 3GPP TS 25.212Multiplexing and channel coding (FDD, v10.1.0 2. 3GPP TS 36.212Multiplexing and channel codin, v10.3.0 3. C. Berrou, A. Glavieux, and P. Thitimajshima, Near Shannon Limit Error-correcting Coding and Decoding Turbo Codes, IEEE Proc 1993 Int Conf. Comm., pp1064-1070 3GPP Mixed Mode Turbo Decoder v2.0 2 Send Feedback PB009 (v2.0) February 4, 2021 www.xilinx.com