50G IEEE 802.3 Reed-Solomon FEC v1.0 PB039 (v1.0) October 5, 2016 LogiCORE IP Product Brief LogiCORE IP Facts Table Introduction Core Specifics The Xilinx LogiCORE 50G IEEE 802.3 Supported UltraScale+ Reed-Solomon Forward Error Correction IP core (1) Device Family Virtex UltraScale implements the Reed-Solomon Forward Error Supported User AXI4-Lite, Configuration and Status bus Correction (RS-FEC) sublayer as described in Interfaces the 25/50G Ethernet Consortium Schedule 3 Provided with Core (v1.6) section 3.2.3 Ref 1 . Design Files Encrypted RTL Example Design Verilog Additional Documentation Test Bench Not Provided Constraints File Xilinx Constraints File A product guide is available for this core. Simulation Access to this material can be requested by Encrypted Verilog Model clicking on this registration link: Supported www.xilinx.com/member/50g rs fec.html N/A S/W Driver (2) Tested Design Flows Features Design Entry Vivado Design Suite Low latency design For supported simulators, see the Simulation Xilinx Design Tools: Release Notes Guide. Configuration and status bus Synthesis Vivado Design Suite Selectable AXI4-Lite interface for status Support output Provided by Xilinx at the Xilinx Support web page Example reference design demonstrating Notes: the use of the core with the GTY 1. For a complete listing of supported devices, see the Vivado IP transceivers catalog. 2. For the supported versions of the tools, see the ECC RAM option Xilinx Design Tools: Release Notes Guide. Copyright 2016 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. AMBA, AMBA Designer, ARM, ARM1176JZ-S, CoreSight, Cortex, and PrimeCell are trademarks of ARM in the EU and other countries. All other trademarks are the property of their respective owners. 50G IEEE 802.3 RS-FEC (v1.0) 1 Send Feedback PB039 (v1.0) October 5, 2016 www.xilinx.comProduct Brief Overview The RS-FEC layers of the 25/50G Ethernet Consortium Schedule 3 Ref 1 define more than just the RS encoder/decoder. They define several stages of synchronization, alignment and transcoding which are necessary for the layer to communicate with preceding and subsequent layers. The functional block diagram of the core is shown in Figure 1. X-Ref Target - Figure 1 OLJQPHQW 7UDQVFRGH &:0 &:0 0DSSLQJ 7UDQVFRGH 0DSSLQJ 5HPRYDO 5HHG 6RORPRQ &:0 ,QVHUWLRQ HFRGHU OLJQPHQW 5HHG 6RORPRQ /RFN DQG (QFRGHU H VNHZ Figure 1: Core Block Diagram Technical Support Xilinx provides technical support at the Xilinx Support web page for this LogiCORE IP product when used as described in the product documentation. Xilinx cannot guarantee timing, functionality, or support if you do any of the following: Implement the solution in devices that are not defined in the documentation. Customize the solution beyond that allowed in the product documentation. Change any section of the design labeled DO NOT MODIFY. To contact Xilinx Technical Support, navigate to the Xilinx Support web page. 50G IEEE 802.3 RS-FEC (v1.0) 2 Send Feedback PB039 (v1.0) October 5, 2016 www.xilinx.com