EF-DI-LDPC-ENC-DEC-SITE Xilinx

LDPC Encoder/Decoder v2.0 PB052 (v2.0) February 8, 2021 LogiCORE IP Product Brief IP Facts The LDPC Encoder/Decoder supports Low Density Parity Check (LDPC) decoding and encoding. The LDPC codes used are highly configurable, and the specific code used can be specified on a codeword-by-codeword basis. Additional Documentation A Product Guide is available for this core. Access to this material can be requested by clicking on this registration link: LDPC Encoder/Decoder v2.0 Number of iterations between 1 and 63 Specified for each block using the AXI4-Stream control interface Early termination Specified for each block to be none, one, or both of the following: - Parity check passes - No change in hard information or parity bits since last iteration When configured as a decoder, soft or hard outputs Specified for each block to include information and optional parity 6-bit soft log-likelihood ratio (LLR) input (8-bit interface, two fractional bits, with external saturation before input to symmetric range -7.75 to +7.75 assumed) and 8-bit output In- or out-of-order execution of blocks, with user specified ID field to identify blocks Encoder and decoder variants, with optional support for improved throughput when sub- matrix size is small Optional final parity check to update parity pass/fail for final output Optional initialization of codes from device configuration, avoiding download using AXI4-Lite interface Interfaces Wide data interfaces on input and output Ability to specify number of inputs and outputs on either a block-by-block basis or transfer basis Separate inputs to specify control parameters and receive status output on a block-by-block basis PB052 (v2.0) February 8, 2021 www.xilinx.com Send Feedback LogiCORE IP Product Brief 2