EF-DI-MIPI-CSI-RX-SITE Xilinx

MIPI D-PHY v4.1 LogiCORE IP Product Guide Vivado Design Suite PG202 (v4.1) July 2, 2019Table of Contents Chapter 1: Introduction.............................................................................................. 4 Features........................................................................................................................................4 IP Facts..........................................................................................................................................5 Chapter 2: Overview......................................................................................................6 Feature Summary........................................................................................................................6 Applications..................................................................................................................................7 Unsupported Features................................................................................................................7 Licensing and Ordering.............................................................................................................. 7 Chapter 3: Product Specification........................................................................... 8 Standards..................................................................................................................................... 8 MIPI D-PHY TX (Master) Core Architecture.............................................................................. 8 MIPI D-PHY RX (Slave) Core Architecture...............................................................................10 Performance.............................................................................................................................. 12 Resource Use............................................................................................................................. 14 Port Descriptions.......................................................................................................................14 Register Space........................................................................................................................... 23 Chapter 4: Designing with the Core................................................................... 29 General Design Gudelines........................................................................................................29 Shared Logic.............................................................................................................................. 30 I/O Planning...............................................................................................................................35 Clocking...................................................................................................................................... 38 Resets..........................................................................................................................................42 Protocol Description................................................................................................................. 45 Chapter 5: Design Flow Steps.................................................................................55 Customizing and Generating the Core...................................................................................55 Constraining the Core...............................................................................................................62 Simulation.................................................................................................................................. 64 Synthesis and Implementation................................................................................................64 PG202 (v4.1) July 2, 2019 www.xilinx.com Send Feedback MIPI D-PHY v4.1 2