0 R XA2C128 CoolRunner-II Automotive CPLD 00 DS554 (v1.2) June 9, 2009 Product Specification Refer to the CoolRunner-II Automotive CPLD family data Features sheet for architecture description. AEC-Q100 device qualification and full PPAP support WARNING: Programming temperature range of available in both I-grade and extended temperature T = 0 C to +70 C. Q-grade A Guaranteed to meet full electrical specifications over Description T = 40C to +105C with T Maximum = +125C A J (Q-grade) The CoolRunner-II Automotive 128-macrocell device is designed for both high performance and low power applica- Optimized for 1.8V systems tions. This lends power savings to high-end communication Industrys best 0.18 micron CMOS CPLD equipment and high speed to battery operated devices. Due - Optimized architecture for effective logic synthesis to the low power stand-by and dynamic operation, overall - Multi-voltage I/O operation 1.5V to 3.3V system reliability is improved. Available in the following package options This device consists of eight Function Blocks inter-con- - 100-pin VQFP with 80 user I/O nected by a low power Advanced Interconnect Matrix (AIM). - 132-ball CP (0.5 mm) BGA with 100 user I/O The AIM feeds 40 true and complement inputs to each - Pb-free only for all packages Function Block. The Function Blocks consist of a 40 by 56 Advanced system features P-term PLA and 16 macrocells which contain numerous - Fastest in system programming configuration bits that allow for combinational or registered 1.8V ISP using IEEE 1532 (JTAG) interface modes of operation. - IEEE1149.1 JTAG Boundary Scan Test Additionally, these registers can be globally reset or preset - Optional Schmitt-trigger input (per pin) and configured as a D or T flip-flop or as a D latch. There - Unsurpassed low power management are also multiple clock signals, both global and local product DataGATE enable (DGE) signal control term types, configured on a per macrocell basis. Output pin - Two separate I/O banks configurations include slew rate limit, bus hold, pull-up, - RealDigital 100% CMOS product term generation open drain and programmable grounds. A Schmitt-trigger - Flexible clocking modes input is available on a per input pin basis. In addition to stor- Optional DualEDGE triggered registers ing macrocell output states, the macrocell registers may be Clock divider (divide by 2,4,6,8,10,12,14,16) configured as direct input registers to store signals directly CoolCLOCK from input pins. - Global signal options with macrocell control Multiple global clocks with phase selection per Clocking is available on a global or Function Block basis. macrocell Three global clocks are available for all Function Blocks as a Multiple global output enables synchronous clock source. Macrocell registers can be indi- Global set/reset vidually configured to power up to the zero or one state. A - Advanced design security global set/reset control line is also available to asynchro- - Open-drain output option for Wired-OR and LED nously set or reset selected registers during operation. drive Additional local clock, synchronous clock-enable, asynchro- - PLA architecture nous set/reset and output enable signals can be formed Superior pinout retention using product terms on a per-macrocell or per-Function 100% product term routability across function Block basis. block A DualEDGE flip-flop feature is also available on a per mac- - Optional bus-hold, 3-state or weak pull-up on rocell basis. This feature allows high performance synchro- selected I/O pins nous operation based on lower frequency clocking to help - Optional configurable grounds on unused I/Os reduce the total power consumption of the device. - Mixed I/O voltages compatible with 1.5V, 1.8V, 2.5V, and 3.3V logic levels Circuitry has also been included to divide one externally - Hot pluggable supplied global clock (GCK2) by eight different selections. This yields divide by even and odd clock frequencies. 20062009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. DS554 (v1.2) June 9, 2009 www.xilinx.com Product Specification 1R XA2C128 CoolRunner-II Automotive CPLD The use of the clock divide (division by 2) and DualEDGE Due to this technology, Xilinx CoolRunner-II Automotive flip-flop gives the resultant CoolCLOCK feature. CPLDs achieve both high-performance and low power oper- ation. DataGATE is a method to selectively disable inputs of the CPLD that are not of interest during certain points in time. Supported I/O Standards By mapping a signal to the DataGATE function, lower power can be achieved due to reduction in signal switching. The CoolRunner-II Automotive 128-macrocell device fea- tures LVCMOS and LVTTL I/O implementations. See Another feature that eases voltage translation is I/O bank- Table 1 for I/O standard voltages. The LVTTL I/O standard is ing. Two I/O banks are available on the CoolRunner-II Auto- a general purpose EIA/JEDEC standard for 3.3V applica- motive 128-macrocell device that permit easy interfacing to tions that use an LVTTL input buffer and Push-Pull output 3.3V, 2.5V, 1.8V, and 1.5V devices. buffer. The LVCMOS standard is used in 3.3V, 2.5V, 1.8V The CoolRunner-II Automotive 128-macrocell CPLD is I/O applications. compatible with various JEDEC I/O standards (see Table 1). This device is also 1.5V I/O compatible with the Table 1: I/O Standards for XA2C128 use of Schmitt-trigger inputs. IOSTANDARD Attribute Output V Input V CCIO CCIO LVTTL 3.3 3.3 RealDigital Design Technology LVCMOS33 3.3 3.3 Xilinx CoolRunner-II Automotive CPLDs are fabricated on a LVCMOS25 2.5 2.5 0.18 micron process technology which is derived from lead- ing edge FPGA product development. CoolRunner-II Auto- LVCMOS18 1.8 1.8 motive CPLDs employ RealDigital technology, a design (1) LVCMOS15 1.5 1.5 technique that makes use of CMOS technology in both the Notes: fabrication and design methodology. RealDigital technology 1. LVCMOS15 requires use of Schmitt-trigger inputs. employs a cascade of CMOS gates to implement sum of products instead of traditional sense amplifier methodology. 20 10 0 50 100 150 0 Frequency (MHz) DS554 01 052109 Figure 1: I vs Frequency CC (1) Table 2: I vs Frequency (LVCMOS 1.8V T = 25C) CC A Frequency (MHz) 0 255075 100 150 Typical I (mA) 0.019 3.97 7.95 11.92 15.89 23.83 CC Notes: 1. 16-bit up/down, Resetable binary counter (one counter per function block). DS554 (v1.2) June 9, 2009 www.xilinx.com Product Specification 2 I (mA) CC