0 R CoolRunner-II Automotive CPLD Product Family 00 DS315 (v1.1) October 31, 2006 Product Specification - Open-drain output option for Wired-OR and LED Features drive AEC-Q100 device qualification and full PPAP support - Optional bus-hold, 3-state or weak pullup on select available in both I-grade and extended temperature I/O pins Q-grade - Optional configurable grounds on unused I/Os Guaranteed to meet full electrical specifications over - Mixed I/O voltages compatible with 1.5V, 1.8V, T = -40 C to +105 C with T Maximum = +125 C A J 2.5V, and 3.3V logic levels on all parts (Q-grade) - Hot pluggable Optimized for 1.8V systems PLA architecture - Industrys fastest low power CPLD - Superior pinout retention - Densities from 32 to 384 macrocells - 100% product term routability across function block Industrys best 0.18 micron CMOS CPLD Wide package availability including fine pitch: - Optimized architecture for effective logic synthesis - Chip Scale BGA, TQFP, and VQFP packages - Multi-voltage I/O operation 1.5V to 3.3V - XA devices use Pb-free packages - Guaranteed 1,000 program/erase cycles Design entry/verification using Xilinx and industry - Guaranteed 20 year data retention standard CAE tools Advanced system features Free software support for all densities using Xilinx - Fastest in system programming WebPACK 1.8V ISP using IEEE 1532 (JTAG) interface - IEEE1149.1 JTAG Boundary Scan Test WARNING: Programming temperature range of - Optional Schmitt trigger input (per pin) T = 0 C to +70 C A - Multiple I/O banks on all devices Family Overview - Unsurpassed low power management Xilinx CoolRunner-II Automotive CPLDs deliver the high DataGATE external signal control - Flexible clocking modes speed and ease of use associated with the XA9500XL Optional DualEDGE triggered registers CPLD family, along with extremely low power versatility in a Clock divider ( 2,4,6,8,10,12,14,16) single CPLD. This means that the exact same parts can be CoolCLOCK used for high-speed data communications/ computing sys- - Global signal options with macrocell control tems and leading edge portable products, with the added Multiple global clocks with phase selection per benefit of In System Programming. Low power consumption macrocell and high-speed operation are combined into a single family Multiple global output enables that is easy to use and cost effective. Clocking techniques Global set/reset and other power saving features extend the users power - Abundant product term clocks, output enables and budget. The design features are supported with Xilinx ISE set/resets WebPACK. Additional details can be found in Further - Efficient control term clocks, output enables and Reading, page 13. set/resets for each macrocell and shared across Table 1 shows the macrocell capacity and key timing function blocks parameters for the CoolRunner-II Automotive CPLD family. - Advanced design security Table 1: CoolRunner-II Automotive CPLD Family Parameters XA2C32A XA2C64A XA2C128 XA2C256 XA2C384 Macrocells 32 64 128 256 384 Max I/O 33 64 100 118 118 T (ns) 5.5 6.7 7.0 7.0 9.2 PD T (ns) 2.6 2.5 3.0 2.8 3.3 SU T (ns) 4.7 6.0 5.4 6.0 7.9 CO F (MHz) 200 159 152 152 125 SYSTEM1 2004-2006 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at R CoolRunner-II Automotive CPLD Product Family Table 2 shows the CoolRunner-II Automotive CPLD pack- CMOS technology used in CoolRunner-II Automotive age offering with corresponding I/O count. All packages are CPLDs generates minimal heat, allowing the use of tiny surface mount, and the ultra tiny packages permit maximum packages during high-speed operation. functional capacity in the smallest possible area. The Table 2: CoolRunner-II Automotive CPLD Family Packages and I/O Count XA2C32A XA2C64A XA2C128 XA2C256 XA2C384 VQG44 33 33 - - - VQG100 - 64 80 80 - CPG132 - - 100 - - TQG144 - - - 118 118 Table 3 details the distribution of advanced features across rocell parts, but very likely for the 384 macrocell part. The the CoolRunner-II Automotive CPLD family. The family has I/O banks are groupings of I/O pins using any one of a sub- uniform basic features with advanced features included in set of compatible voltage standards that share the same densities where they are most useful. For example, it is very V level. (See Table 4 for a summary of CoolRunner-II CCIO unlikely that four I/O banks are needed on 32 and 64 mac- Automotive CPLD I/O standards.) Table 3: CoolRunner-II Automotive CPLD Family Features XA2C32A XA2C64A XA2C128 XA2C256 XA2C384 IEEE 1532 I/O banks 2 2 2 2 4 Clock division - - DualEDGE Registers DataGATE - - LVTTL LVCMOS33, 25, 18, and (1) 15 Configurable ground Quadruple data security Open drain outputs Hot plugging Schmitt Inputs 1. LVCMOS15 requires the use of Schmitt-trigger inputs. ware, which exploits the 100% routability of the Program- Architecture Description mable Logic Array within each FB. This extremely robust CoolRunner-II Automotive CPLD is a highly uniform family building block delivers the industrys highest pinout reten- of fast, low power CPLDs. The underlying architecture is a tion, under very broad design conditions. The architecture traditional CPLD architecture combining macrocells into will be explained by expanding the detail as we discuss the Function Blocks (FBs) interconnected with a global routing underlying Function Blocks, logic and interconnect. matrix, the Xilinx Advanced Interconnect Matrix (AIM). The The design software automatically manages these device Function Blocks use a Programmable Logic Array (PLA) resources so that users can express their designs using configuration which allows all product terms to be routed completely generic constructs without knowledge of these and shared among any of the macrocells of the FB. Design architectural details. More advanced users can take advan- software can efficiently synthesize and optimize logic that is tage of these details to more thoroughly understand the subsequently fit to the FBs and connected with the ability to softwares choices and direct its results. utilize a very high percentage of device resources. Design changes are easily and automatically managed by the soft- 2 www.xilinx.com DS315 (v1.1) October 31, 2006 Product Specification