37 R XA Spartan-3E Automotive FPGA Family Data Sheet 0 DS635 (v2.0) September 9, 2009 Product Specification Summary The Xilinx Automotive (XA) Spartan-3E family of FPGAs - Enhanced Double Data Rate (DDR) support is specifically designed to meet the needs of high-volume, - DDR SDRAM support up to 266 Mb/s cost-sensitive automotive electronics applications. The Abundant, flexible logic resources five-member family offers densities ranging from 100,000 to - Densities up to 33,192 logic cells, including 1.6 million system gates, as shown in Table 1. optional shift register or distributed RAM support - Efficient wide multiplexers, wide logic Introduction - Fast look-ahead carry logic XA devices are available in both extended-temperature - Enhanced 18 x 18 multipliers with optional pipeline Q-Grade (40C to +125C T ) and I-Grade (40C to J - IEEE 1149.1/1532 JTAG programming/debug port +100C T ) and are qualified to the industry recognized J Hierarchical SelectRAM memory architecture AEC-Q100 standard. - Up to 648 Kbits of fast block RAM The XA Spartan-3E family builds on the success of the ear- - Up to 231 Kbits of efficient distributed RAM lier XA Spartan-3 family by increasing the amount of logic Up to eight Digital Clock Managers (DCMs) per I/O, significantly reducing the cost per logic cell. New - Clock skew elimination (delay locked loop) features improve system performance and reduce the cost - Frequency synthesis, multiplication, division of configuration. These XA Spartan-3E FPGA enhance- - High-resolution phase shifting ments, combined with advanced 90 nm process technology, - Wide frequency range (5 MHz to over 300 MHz) deliver more functionality and bandwidth per dollar than was Eight global clocks plus eight additional clocks per previously possible, setting new standards in the program- each half of device, plus abundant low-skew routing mable logic industry. Configuration interface to industry-standard PROMs Because of their exceptionally low cost, XA Spartan-3E - Low-cost, space-saving SPI serial Flash PROM FPGAs are ideally suited to a wide range of automotive - x8 or x8/x16 parallel NOR Flash PROM applications, including infotainment, driver information, and driver assistance modules. Complete Xilinx ISE and WebPACK software support The XA Spartan-3E family is a superior alternative to mask MicroBlaze and PicoBlaze embedded processor programmed ASICs and ASSPs. FPGAs avoid the high ini- cores tial mask set costs and lengthy development cycles, while also permitting design upgrades in the field with no hard- Fully compliant 32-/64-bit 33 MHz PCI technology ware replacement necessary because of its inherent pro- support grammability, an impossibility with conventional ASICs and Low-cost QFP and BGA packaging options ASSPs with their inflexible hardware architecture. - Common footprints support easy density migration Refer to Spartan-3E FPGA Family: Complete Data Sheet Features (DS312) for a full product description, AC and DC specifica- Very low-cost, high-performance logic solution for tions, and package pinout descriptions. Any values shown high-volume automotive applications specifically in this XA Spartan-3E Automotive FPGA Family data sheet override those shown in DS312. Proven advanced 90-nanometer process technology Multi-voltage, multi-standard SelectIO interface pins For information regarding reliability qualification, refer to - Up to 376 I/O pins or 156 differential signal pairs RPT081 (Xilinx Spartan-3E Family Automotive Qualification Report) and RPT012 (Spartan-3/3E UMC-12A 90 nm Qual- - LVCMOS, LVTTL, HSTL, and SSTL single-ended ification Report). signal standards - 3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling - 622+ Mb/s data transfer rate per I/O - True LVDS, RSDS, mini-LVDS, differential HSTL/SSTL differential I/O 20072009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI, PCIe, and PCI Express are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners. DS635 (v2.0) September 9, 2009 www.xilinx.com Product Specification 1R Key Feature Differences from Commercial XC Devices AEC-Q100 device qualification and full production part Spartan-3E FPGA product line. approval process (PPAP) documentation support XA Spartan-3E devices are available in Step 1 only. available in both extended temperature I- and JTAG configuration frequency reduced from 30 MHz to Q-Grades 25 MHz. Guaranteed to meet full electrical specification over the Platform Flash is not supported within the XA family. T = 40C to +125C temperature range (Q-Grade) J XA Spartan-3E devices are available in Pb-free XA Spartan-3E devices are available in the -4 speed packaging only. grade only. MultiBoot is not supported in XA versions of this PCI-66 is not supported in the XA Spartan-3E FPGA product. product line. The XA Spartan-3E device must be power cycled prior The readback feature is not supported in the XA to reconfiguration. Table 1: Summary of XA Spartan-3E FPGA Attributes CLB Array (One CLB = Four Slices) Equivalent Block Maximum System Logic Total Total Distributed RAM Dedicated Maximum Differential (1) (1) Device Gates Cells Rows Columns CLBs Slices RAM bits bits Multipliers DCMs User I/O I/O Pairs XA3S100E 100K 2,160 22 16 240 960 15K 72K 4 2 108 40 250K 5,508 34 26 612 2,448 38K 216K 12 4 172 68 XA3S250E 500K 10,476 46 34 1,164 4,656 73K 360K 20 4 190 77 XA3S500E 1200K 19,512 60 46 2,168 8,672 136K 504K 28 8 304 124 XA3S1200E XA3S1600E 1600K 33,192 76 58 3,688 14,752 231K 648K 36 8 376 156 Notes: 1. By convention, one Kb is equivalent to 1,024 bits. Architectural Overview The XA Spartan-3E family architecture consists of five fun- Digital Clock Manager (DCM) Blocks provide damental programmable functional elements: self-calibrating, fully digital solutions for distributing, delaying, multiplying, dividing, and phase-shifting clock Configurable Logic Blocks (CLBs) contain flexible signals. Look-Up Tables (LUTs) that implement logic plus storage elements used as flip-flops or latches. CLBs These elements are organized as shown in Figure 1. A ring perform a wide variety of logical functions as well as of IOBs surrounds a regular array of CLBs. Each device has store data. two columns of block RAM except for the XA3S100E, which has one column. Each RAM column consists of several Input/Output Blocks (IOBs) control the flow of data 18-Kbit RAM blocks. Each block RAM is associated with a between the I/O pins and the internal logic of the dedicated multiplier. The DCMs are positioned in the center device. Each IOB supports bidirectional data flow plus with two at the top and two at the bottom of the device. The 3-state operation. Supports a variety of signal XA3S100E has only one DCM at the top and bottom, while standards, including four high-performance differential the XA3S1200E and XA3S1600E add two DCMs in the mid- standards. Double Data-Rate (DDR) registers are dle of the left and right sides. included. Block RAM provides data storage in the form of The XA Spartan-3E family features a rich network of traces 18-Kbit dual-port blocks. that interconnect all five functional elements, transmitting signals among them. Each functional element has an asso- Multiplier Blocks accept two 18-bit binary numbers as ciated switch matrix that permits multiple connections to the inputs and calculate the product. routing. DS635 (v2.0) September 9, 2009 www.xilinx.com Product Specification 2