0<BL Blue> R XA Spartan-3 Automotive FPGA Family: Introduction and Ordering Information 00 DS314 (v1.3) June 18, 2009 Product Specification Summary The Xilinx Automotive (XA) Spartan-3 family of Field-Programmable Gate Arrays meets the needs of high-volume, cost-sensitive automotive electronic applications. The five-member family offers densities ranging from 50,000 to 1.5 million system gates, as shown in Table 1. Introduction Features AEC-Q100 device qualification and full PPAP XA devices are available in both extended-temperature documentation support available in both extended Q-grade (40C to +125C T ) and I-grade (40C to J temperature Q-grade and I-grade +100C T ) and are qualified to the industry-recognized J AEC-Q100 standard. Guaranteed to meet full electrical specification over the T = 40C to +125C temperature range J The XA Spartan-3 family builds on the success of the earlier XA Spartan-IIE family by increasing the amount of logic Revolutionary 90-nanometer process technology resources, the capacity of internal RAM, the total number of Low cost, high-performance logic solution for I/Os, and the overall level of performance as well as by high-volume, automotive applications improving clock management functions. These Spartan-3 Three power rails: for core (1.2V), I/Os (1.2V to enhancements, combined with advanced process 3.3V), and auxiliary purposes (2.5V) technology, deliver more functionality and bandwidth per dollar than was previously possible, setting new standards SelectIO interface signaling in the programmable logic industry. Up to 487 I/O pins Because of their exceptionally low cost, Spartan-3 FPGAs 622 Mb/s data transfer rate per I/O are ideally suited to a wide range of advanced automotive Eighteen single-ended signal standards electronics modules and systems ranging from the latest Eight differential signal standards including LVDS driver assistance and infotainment systems to instrument clusters and gateways. Termination by Digitally Controlled Impedance The Spartan-3 family is a flexible alternative to ASICs, Signal swing ranging from 1.14V to 3.45V ASSPs, and microcontrollers. FPGAs avoid the high initial Double Data Rate (DDR) support NREs, the lengthy development cycles, and problems with Logic resources obsolescence. Also, FPGA programmability permits design upgrades in the field with no hardware replacement Abundant logic cells with shift register capability necessary. Wide multiplexers Table 1: Summary of Spartan-3 FPGA Attributes CLB Array Maximum (One CLB = Four Slices) System Logic Distributed Block RAM Dedicated Maximum Differential 1 1 Device Gates Cells Rows Columns Total CLBs RAM (bits ) (bits ) Multipliers DCMs User I/O I/O Pairs XA3S50 50K 1,728 16 12 192 12K 72K 4 2 124 56 XA3S200 200K 4,320 24 20 480 30K 216K 12 4 173 76 XA3S400 400K 8,064 32 28 896 56K 288K 16 4 264 116 XA3S1000 1M 17,280 48 40 1,920 120K 432K 24 4 333 149 3,328 XA3S1500 1.5M 29,952 64 52 208K 576K 32 4 487 221 Notes: 1. By convention, one Kb is equivalent to 1,024 bits. 20042009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. HyperTransport is a licensed trademark of the HyperTransport Technology Consortium in the U.S. and other jurisdictions. All other trademarks are the property of their respective owners. DS314 (v1.3) June 18, 2009 www.xilinx.com Product Specification 1R Introduction and Ordering Information Fast look-ahead carry logic elements that can be used as flip-flops or latches. CLBs can be programmed to perform a wide variety of Dedicated 18 x 18 multipliers logical functions as well as to store data. JTAG logic compatible with IEEE 1149.1/1532 Input/Output Blocks (IOBs) control the flow of data SelectRAM hierarchical memory between the I/O pins and the internal logic of the Up to 576 Kbits of total block RAM device. Each IOB supports bidirectional data flow plus 3-state operation. Twenty-six different signal standards, Up to 208 Kbits of total distributed RAM including eight high-performance differential standards, Digital Clock Manager (up to four DCMs) are available as shown in Table 2. Double Data-Rate Clock skew elimination (DDR) registers are included. The Digitally Controlled Impedance (DCI) feature provides automatic on-chip Frequency synthesis terminations, simplifying board designs. High-resolution phase shifting Block RAM provides data storage in the form of 18-Kbit Maximum clock frequency 125 MHz dual-port blocks. Fully supported by Xilinx ISE software development Multiplier blocks accept two 18-bit binary numbers as system inputs and calculate the product. Synthesis, mapping, placement and routing Digital Clock Manager (DCM) blocks provide MicroBlaze processor, CAN, LIN, MOST, and other self-calibrating, fully digital solutions for distributing, cores delaying, multiplying, dividing, and phase shifting clock signals. Pb-free packaging options These elements are organized as shown in Figure 1. A ring Xilinx and all of our production partners are qualified to of IOBs surrounds a regular array of CLBs. The XA3S50 ISO-TS16949 has a single column of block RAM embedded in the array. Please refer to the Spartan-3 complete data sheet (DS099) Those devices ranging from the XA3S200 to the XA3S1500 for a full product description, AC and DC specifications, and have two columns of block RAM. Each column is made up package pinout descriptions of several 18 Kbit RAM blocks each block is associated with a dedicated multiplier. The DCMs are positioned at the ends of the block RAM columns. Architectural Overview The Spartan-3 family features a rich network of traces and The Spartan-3 family architecture consists of five switches that interconnect all five functional elements, fundamental programmable functional elements: transmitting signals among them. Each functional element has an associated switch matrix that permits multiple Configurable Logic Blocks (CLBs) contain RAM-based connections to the routing. Look-Up Tables (LUTs) to implement logic and storage DS314 (v1.3) June 18, 2009 www.xilinx.com Product Specification 2