0 R XA95144XL Automotive CPLD 00 DS600 (v1.1) April 3, 2007 Product Specification gates with propagation delays of 15.5 ns. See Figure 2 for Features overview. AEC-Q100 device qualification and full PPAP support Power Estimation available in I-grade. Power dissipation in CPLDs can vary substantially depend- Guaranteed to meet full electrical specifications over ing on the system frequency, design application and output T = -40 C to +85 C (I-grade) A loading. Each macrocell in an XA9500XL automotive device 15.5 ns pin-to-pin logic delays must be configured for low-power mode (default mode for System frequency up to 64.5 MHz XA9500XL devices). In addition, unused product-terms and 144 macrocells with 3,200 usable gates macrocells are automatically deactivated by the software to Available in the following package further conserve power. - 144-CSP (117 user I/O pins) For a general estimate of I , the following equation may be - Pb-free package only CC used: Optimized for high-performance 3.3V systems - Low power operation I (mA) = MC(0.052*PT + 0.272) + 0.04 * MC * MC * f CC TOG - 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V where: signals - 3.3V or 2.5V output capability MC = macrocells - Advanced 0.35 micron feature size CMOS PT = average number product terms per macrocell Fast FLASH technology Advanced system features f = maximum clock frequency - In-system programmable MC = average % of flip-flops toggling per clock TOG - Superior pin-locking and routability with (~12%) Fast CONNECT II switch matrix - Extra wide 54-input Function Blocks This calculation was derived from laboratory measurements - Up to 90 product-terms per macrocell with of an XA9500XL part filled with 16-bit counters and allowing individual product-term allocation a single output (the LSB) to be enabled. The actual I CC - Local clock inversion with three global and one value varies with the design application and should be veri- product-term clocks fied during normal system operation. Figure 1 shows the - Individual output enable per output pin with local above estimation in a graphical form. For a more detailed inversion discussion of power consumption in this device, see Xilinx - Input hysteresis on all user and boundary-scan pin application note XAPP114, Understanding XC9500XL inputs CPLD Power. - Bus-hold circuitry on all user pin inputs 150 - Full IEEE Standard 1149.1 boundary-scan (JTAG) Fast concurrent programming 100 Slew rate control on individual outputs Enhanced data security features 64.4 MHz Excellent quality and reliability 50 - Endurance exceeding 10,000 program/erase cycles 0 - 20 year data retention 50 100 Clock Frequency (MHz) DS600 01 121106 - ESD protection exceeding 2,000V WARNING: Programming temperature range of Figure 1: Typical I vs. Frequency for XA95144XL CC T = 0 C to +70 C A Description The XA95144XL is a 3.3V CPLD targeted for high-perfor- mance, low-voltage automotive applications. It is comprised of eight 54V18 Function Blocks, providing 3,200 usable 2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at R XA95144XL Automotive CPLD 3 JTAG In-System Programming Controller 1 JTAG Port Controller 54 Function 18 Block 1 I/O Macrocells I/O 1 to 18 I/O 54 I/O Function 18 Block 2 Macrocells 1 to 18 I/O Blocks I/O 54 Function I/O 18 Block 3 Macrocells I/O 1 to 18 I/O 3 I/O/GCK 54 Function 1 18 Block 4 I/O/GSR 4 Macrocells I/O/GTS 1 to 18 54 Function 18 Block 8 Macrocells 1 to 18 DS056 02 101300 Figure 2: XA95144XL Architecture Function Block outputs (indicated by the bold line) drive the I/O Blocks directly. 2 www.xilinx.com DS600 (v1.1) April 3, 2007 Product Specification Fast CONNECT II Switch Matrix