0 R XA9536XL Automotive CPLD 00 DS598 (v1.1) April 3, 2007 Product Specification of two 54V18 Function Blocks, providing 800 usable gates Features with propagation delays of 15.5 ns. See Figure 2 for archi- AEC-Q100 device qualification and full PPAP support tecture overview. available in both extended temperature Q-grade and I-grade. Power Estimation Guaranteed to meet full electrical specifications over Power dissipation in CPLDs can vary substantially depend- T = -40 C to +105 C with T Maximum = +125 C A J ing on the system frequency, design application and output (Q-grade) loading. Each macrocell in an XA9500XL automotive device 15.5 ns pin-to-pin logic delays must be configured for low-power mode (default mode for System frequency up to 64.5 MHz XA9500XL devices). In addition, unused product-terms and 36 macrocells with 800 usable gates macrocells are automatically deactivated by the software to Available in small footprint packages further conserve power. - 44-pin VQFP (34 user I/O pins) For a general estimate of I , the following equation may be CC - Pb-free package only used: Optimized for high-performance 3.3V systems I (mA) = MC(0.052*PT + 0.272) + 0.04 * MC *MC* f CC TOG - Low power operation - 5V tolerant I/O pins accept 5 V, 3.3V, and 2.5V where: signals MC = macrocells - 3.3V or 2.5V output capability - Advanced 0.35 micron feature size CMOS PT = average number of product terms per macrocell Fast FLASH technology f = maximum clock frequency Advanced system features - In-system programmable MC = average % of flip-flops toggling per clock TOG - Superior pin-locking and routability with (~12%) Fast CONNECT II switch matrix This calculation was derived from laboratory measurements - Extra wide 54-input Function Blocks of an XA9500XL part filled with 16-bit counters and allowing - Up to 90 product-terms per macrocell with a single output (the LSB) to be enabled. The actual I CC individual product-term allocation value varies with the design application and should be veri- - Local clock inversion with three global and one fied during normal system operation. Figure 1 shows the product-term clocks above estimation in a graphical form. For a more detailed - Individual output enable per output pin discussion of power consumption in this device, see Xilinx - Input hysteresis on all user and boundary-scan pin application note XAPP114, Understanding XC9500XL inputs CPLD Power. - Bus-hold circuitry on all user pin inputs - Full IEEE Standard 1149.1 boundary-scan (JTAG) Fast concurrent programming 30 64.5 MHz Slew rate control on individual outputs 20 Enhanced data security features Excellent quality and reliability 10 - Endurance exceeding 10,000 program/erase cycles - 20 year data retention 0 50 100 - ESD protection exceeding 2,000V Clock Frequency (MHz) DS598 01 121106 WARNING: Programming temperature range of Figure 1: Typical I vs. Frequency for XA9536XL CC T = 0 C to +70 C A Description The XA9536XL is a 3.3V CPLD targeted for high-perfor- mance, low-voltage automotive applications. It is comprised 2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at R XA9536XL Automotive CPLD 3 JTAG In-System Programming Controller 1 JTAG Port Controller 54 Function 18 Block 1 I/O Macrocells I/O 1 to 18 I/O 54 I/O Function 18 Block 2 Macrocells 1 to 18 I/O Blocks I/O I/O I/O I/O 3 I/O/GCK 1 I/O/GSR 2 I/O/GTS DS058 02 081500 Figure 2: XA9536XL Architecture Function Block outputs (indicated by the bold line) drive the I/O Blocks directly. 2 www.xilinx.com DS598 (v1.1) April 3, 2007 Product Specification Fast CONNECT II Switch Matrix