1 Spartan-3AN FPGA Family Data Sheet DS557 January 9, 2019 Product Specification Module 1: Module 3: Introduction and Ordering Information DC and Switching Characteristics DS557(v4.3) January 9, 2019 DS557 (v4.3) January 9, 2019 Introduction DC Electrical Characteristics Features Absolute Maximum Ratings Architectural Overview Supply Voltage Specifications Recommended Operating Conditions Configuration Overview In-system Flash Memory Overview Switching Characteristics General I/O Capabilities I/O Timing Supported Packages and Package Marking Configurable Logic Block (CLB) Timing Ordering Information Multiplier Timing Block RAM Timing Module 2: Digital Clock Manager (DCM) Timing Functional Description Suspend Mode Timing Device DNA Timing DS557 (v4.3) January 9, 2019 Configuration and JTAG Timing The functionality of the Spartan-3AN FPGA family is described in the following documents: Module 4: Pinout Descriptions UG331: Spartan-3 Generation FPGA User Guide Clocking Resources DS557 (v4.3) January 9, 2019 Digital Clock Managers (DCMs) Pin Descriptions Block RAM Package Overview Configurable Logic Blocks (CLBs) Pinout Tables - Distributed RAM Footprint Diagrams - SRL16 Shift Registers Table 1: Production Status of Spartan-3AN FPGAs - Carry and Arithmetic Logic I/O Resources Spartan-3AN FPGA Status Embedded Multiplier Blocks XC3S50AN Production Programmable Interconnect ISE Design Tools and IP Cores XC3S200AN Production Embedded Processing and Control Solutions XC3S400AN Production Pin Types and Package Overview Package Drawings XC3S700AN Production Powering FPGAs XC3S1400AN Production Power Management UG332: Spartan-3 Generation Configuration User Guide Additional information on the Spartan-3AN family can be Configuration Overview found at: Configuration Pins and Behavior 9 Spartan-3AN FPGA Family: Introduction and Ordering Information DS557(v4.3) January 9, 2019 Product Specification Introduction The Spartan-3AN FPGA family combines the best attributes of a Buried configuration interface leading edge, low cost FPGA with nonvolatile technology across a Unique Device DNA serial number in each device for broad range of densities. The family combines all the features of design Authentication to prevent unauthorized copying the Spartan-3A FPGA family plus leading technology in-system Flash memory sector protection and lockdown Flash memory for configuration and nonvolatile data storage. Configuration watchdog timer automatically recovers from The Spartan-3AN FPGAs are part of the Extended Spartan-3A configuration errors family, which also includes the Spartan-3A FPGAs and the higher Suspend mode reduces system power consumption density Spartan-3A DSP FPGAs. The Spartan-3AN FPGA family Retains all design state and FPGA configuration data is excellent for space-constrained applications such as blade Fast response time, typically less than 100 s servers, medical devices, automotive infotainment, telematics, Full hot-swap compliance GPS, and other small consumer products. Combining FPGA and Flash technology minimizes chip count, PCB traces and overall Multi-voltage, multi-standard SelectIO interface pins size while increasing system reliability. Up to 502 I/O pins or 227 differential signal pairs The Spartan-3AN FPGA internal configuration interface is LVCMOS, LVTTL, HSTL, and SSTL single-ended signal completely self-contained, increasing design security. The family standards maintains full support for external configuration. The Spartan-3AN 3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling FPGA is the worlds first nonvolatile FPGA with MultiBoot, Up to 24 mA output drive supporting two or more configuration files in one device, allowing 3.3V 10% compatibility and hot swap compliance alternative configurations for field upgrades, test modes, or 622+ Mb/s data transfer rate per I/O multiple system configurations. DDR/DDR2 SDRAM support up to 400 Mb/s Features LVDS, RSDS, mini-LVDS, PPDS, and HSTL/SSTL differential I/O The new standard for low cost nonvolatile FPGA solutions Abundant, flexible logic resources Eliminates traditional nonvolatile FPGA limitations with the Densities up to 25,344 logic cells advanced 90 nm Spartan-3A device feature set Optional shift register or distributed RAM support Memory, multipliers, DCMs, SelectIO, hot swap, power management, etc. Enhanced 18 x 18 multipliers with optional pipeline Integrated robust configuration memory Hierarchical SelectRAM memory architecture Saves board space Up to 576 Kbits of dedicated block RAM Improves ease-of-use Up to 176 Kbits of efficient distributed RAM Simplifies design Up to eight Digital Clock Managers (DCMs) Reduces support issues Eight global clocks and eight additional clocks per each half of device, plus abundant low-skew routing Plentiful amounts of nonvolatile memory available to the user Complete Xilinx ISE and WebPACK software Up to 11+ Mb available development system support MultiBoot support MicroBlaze and PicoBlaze embedded processor cores Embedded processing and code shadowing Fully compliant 32-/64-bit 33 MHz PCI technology support Scratchpad memory Low-cost QFP and BGA Pb-free (RoHS) packaging options Robust 100K Flash memory program/erase cycles Pin-compatible with the same packages in the 20 years Flash memory data retention Spartan-3A FPGA family Security features provide bitstream anti-cloning protection Table 2: Summary of Spartan-3AN FPGA Attributes System Equivalent Distributed Block RAM Dedicated Maximum Max Differential Bitstream In-System (1) (1) (1) Device Gates Logic Cells CLBs Slices RAM Bits Bits Multipliers DCMs User I/O I/O Pairs Size Flash Bits (2) XC3S50AN 50K 1,584 176 704 11K 54K 3 2 108 50 427K 1M XC3S200AN 200K 4,032 448 1,792 28K 288K 16 4 195 90 1,168K 4M XC3S400AN 400K 8,064 896 3,584 56K 360K 20 4 311 142 1,842K 4M XC3S700AN 700K 13,248 1,472 5,888 92K 360K 20 8 372 165 2,669K 8M XC3S1400AN 1400K 25,344 2,816 11,264 176K 576K 32 8 502 227 4,644K 16M Notes: 1. By convention, one Kb is equivalent to 1,024 bits and one Mb is equivalent to 1,024 Kb. 2. Maximum supported by Xilinx tools. See the customer notice XCN14003: Flash Wafer Fabrication Change and Gold (Au) To Copper (Cu) Transition for Spartan-3AN FPGA Devices. Copyright 20072019 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners. DS557(v4.3) January 9, 2019 www.xilinx.com Send Feedback Product Specification 2