0 R XC9536XL High Performance CPLD 00 DS058 (v1.9) April 3, 2007 Product Specification 54V18 Function Blocks, providing 800 usable gates with Features propagation delays of 5 ns. See Figure 2 for architecture 5 ns pin-to-pin logic delays overview. System frequency up to 178 MHz 36 macrocells with 800 usable gates Power Estimation Available in small footprint packages Power dissipation in CPLDs can vary substantially depend- - 44-pin PLCC (34 user I/O pins) ing on the system frequency, design application and output - 44-pin VQFP (34 user I/O pins) loading. To help reduce power dissipation, each macrocell - 48-pin CSP (36 user I/O pins) in a XC9500XL device may be configured for low-power - 64-pin VQFP (36 user I/O pins) mode (from the default high-performance mode). In addi- - Pb-free available for all packages tion, unused product-terms and macrocells are automati- Optimized for high-performance 3.3V systems cally deactivated by the software to further conserve power. - Low power operation For a general estimate of I , the following equation may be CC - 5V tolerant I/O pins accept 5 V, 3.3V, and 2.5V used: signals I (mA) = MC (0.175*PT + 0.345) + MC (0.052*PT CC HS HS LP LP - 3.3V or 2.5V output capability + 0.272) + 0.04 * MC (MC +MC )* f TOG HS LP - Advanced 0.35 micron feature size CMOS where: Fast FLASH technology MC = macrocells in high-speed configuration HS Advanced system features PT = average number of high-speed product terms HS - In-system programmable per macrocell - Superior pin-locking and routability with MC = macrocells in low power configuration LP Fast CONNECT II switch matrix PT = average number of low power product terms per LP - Extra wide 54-input Function Blocks macrocell - Up to 90 product-terms per macrocell with f = maximum clock frequency individual product-term allocation MCTOG = average % of flip-flops toggling per clock - Local clock inversion with three global and one (~12%) product-term clocks - Individual output enable per output pin This calculation was derived from laboratory measurements - Input hysteresis on all user and boundary-scan pin of an XC9500XL part filled with 16-bit counters and allowing inputs a single output (the LSB) to be enabled. The actual I CC - Bus-hold circuitry on all user pin inputs value varies with the design application and should be veri- - Full IEEE Standard 1149.1 boundary-scan (JTAG) fied during normal system operation. Figure 1 shows the Fast concurrent programming above estimation in a graphical form. For a more detailed Slew rate control on individual outputs discussion of power consumption in this device, see Xilinx Enhanced data security features Excellent quality and reliability - Endurance exceeding 10,000 program/erase cycles - 20 year data retention - ESD protection exceeding 2,000V Pin-compatible with 5V-core XC9536 device in the 44-pin PLCC package and the 48-pin CSP package WARNING: Programming temperature range of T = 0 C to +70 C A Description The XC9536XL is a 3.3V CPLD targeted for high-perfor- mance, low-voltage applications in leading-edge communi- cations and computing systems. It is comprised of two 2006 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at R XC9536XL High Performance CPLD application note XAPP114, Understanding XC9500XL CPLD Power. 70 60 178 MHz 50 40 30 125 MHz 20 10 0 100 200 250 50 150 Clock Frequency (MHz) DS058 01 121501 Figure 1: Typical I vs. Frequency for XC9536XL CC 3 JTAG In-System Programming Controller 1 JTAG Port Controller 54 Function 18 Block 1 I/O Macrocells I/O 1 to 18 I/O 54 I/O Function 18 Block 2 Macrocells 1 to 18 I/O Blocks I/O I/O I/O I/O 3 I/O/GCK 1 I/O/GSR 2 I/O/GTS DS058 02 081500 Figure 2: XC9536XL Architecture Function Block outputs (indicated by the bold line) drive the I/O Blocks directly. 2 www.xilinx.com DS058 (v1.9) April 3, 2007 Product Specification High Performance Low Power Typical I (mA) CC Fast CONNECT II Switch Matrix