SKU74 Zipcores

BPSK DEMOD Binary-PSK Demodulator Rev. 2.0 Key Design Features Block Diagram Synthesizable, technology independent IP Core for FPGA, reset mag thresh ASIC and SoC 16 Supplied as human readable VHDL (or Verilog) source code 16-bit signed input data samples 16 SQUARING x in Automatic carrier acquisition with no complex setup required FUNCTION User specified carrier frequency, symbol rate and sample rate SYMBOL Practical symbol rates of up to 10 Mbits/s PEAKING psk val DECODE FILTER AND ( 2 x Carrier Typical FPGA sample rates of up to 200 MHz TIMING psk out Frequency ) RECOVERY Applications LOWPASS FREQUENCY 16 PULSE mag out DIVIDER SHAPING /2 FILTER Software radio en Short to medium-range telemetry PEAKING FILTER IF, SRD and ISM band devices ( 1x Carrier Recovered clk Frequency ) Carrier signal Robust, low bandwidth radio applications for small FPGA devices Low-cost radio links over a few 100 meters using either wireless or cable - e.g. coax or twisted pair Figure 1: Simplified BPSK Demodulator architecture Applications where fast carrier acquisition is essential - e.g. where data packets are transmitted in short discrete bursts General Description Generic Parameters The BPSK DEMOD IP Core (Figure 1) is a 16-bit resolution Binary-PSK demodulator based on a multiply-filter-divide architecture. The design is robust and flexible and allows easy connectivity to an external ADC. Generic name Description Type Valid range As the carrier recovery circuit is open-loop, there is no feedback path or sym period Symbol period in integer 0 to 65535 loop-filter to configure. This results in an extremely simple circuit with a sample clocks very fast carrier acquisition time. The only requirement is that the user must set the desired symbol period and a suitable threshold level for the sym polarity Swaps symbol polarity boolean TRUE / FALSE bit decisions at the symbol decoder. The other design parameters i.e. 1 0 including carrier frequency, symbol rate and sampling frequency should 1 be specified by the user before delivery of the IP Core . Pin-out Description The input data samples are 16-bit signed (2 s complement) values that are synchronous with the system/sample clock. Input values are sampled on the rising edge of clk when en is high. Pin name I/O Description Active state Figure 1 shows the basic architecture in more detail. The input signal is clk in Sample clock rising edge first squared in order to generate a harmonic at twice the carrier frequency and zero phase-shift. This squared signal is then filtered and reset in Asynchronous reset low divided in frequency to recover the original carrier. A second filter is en in Clock enable high employed to isolate a clean carrier signal which is used to demodulate the original input signal. The demodulated input signal then goes through a x in 15:0 in BPSK 16-bit signed input data low-pass pulse-shaping filter before a bit-decision is made at the symbol decoder. mag thresh 15:0 in Bit decision level threshold data for a 0 /1 The demodulated BPSK bit-stream appears at the output psk out. Bits (16-bit unsigned) are valid on the rising edge of clk when both psk val and en are high. mag out 15:0 out Magnitude of symbol data values at the decoder (16-bit signed) psk val out PSK bit valid strobe high 1 Please contact Zipcores first to discuss your design parameters. We can also provide a subset of programmable design parameters if psk out out PSK bit out data necessary. Copyright 2019 www.zipcores.com Download this IP Core Page 1 of 6 sym period sym polarityBPSK DEMOD Binary-PSK Demodulator Rev. 2.0 Peaking Filters The signal path is filtered using a series of peaking filters in order to ND recover the carrier signal. These filters are precision 2 order IIR filters with fully configurable 16-bit coefficients. The coefficients are specified at compile time and should be set correctly for the chosen sample rate and carrier frequency. The characteristics of these filters will largely determine how fast the carrier signal is acquired and how the system responds to jitter and frequency drift between the transmitter and receiver clocks. Figures 2 and 3 below show some example filter responses for a system with a carrier frequency set to 5 MHz. The first peaking filter isolates the 10 MHz tone after squaring. The second peaking filter is used to recover the 5 MHz carrier signal. In both cases (Figure 2 and 3) the sample frequency is set to 125 MHz. Figure 3: Magnitude and Impulse responses for a Figure 2: Magnitude and Impulse responses for a 10 MHz peaking filter (2 x carrier frequency) 5 MHz peaking filter (1 x carrier frequency) Copyright 2019 www.zipcores.com Download this IP Core Page 2 of 6