FLASH CONT Parallel FLASH Memory Controller Rev. 1.1 Key Design Features Block Diagram Synthesizable, technology independent VHDL IP Core 8-bit / 16-bit Flash memory controller with synchronous user interface Provides the physical interface between your FPGA / ASIC and the external Flash memory component JEDEC standard Flash EEPROM pinouts and commands Configurable timing parameters to suit different Flash memory components Configurable command FIFO compensates for System-to-Flash speed differences Wide range of Flash memories supported Vendors such as Microchip, Atmel, AMD, EON and STmicroelectronics Figure 1: Flash memory controller architecture Examples include the SST39*, AT49*, AM29*, EN29* and M29* series Flash memory ICs Pin-out Description Applications Pin name I/O Description Active state Any application where non-volatile storage is required clk in Synchronous clock rising edge reset in Asynchronous reset low Offline storage of parameters and data for FPGA / ASIC flash cmd 1:0 in Flash command bus flash addr 15:0 in Flash address bus Generic Parameters flash data dw-1:0 in Flash write data bus flash val in Flash command valid high Generic name Description Type Valid range 32 flash rdy out Flash command ready high t as Address setup time in integer 0 < t as < 2 (handshake signal) system clock cycles 32 rdata 7:0 out Flash read data in bus t ah Address hold time in integer 0 < t ah < 2 system clock cycles rdata val out Flash read data valid high 32 t wp Write strobe pulse integer 0 < t wp < 2 adn 15:0 out Flash address bus width in system clock dqn dw-1:0 io Bi-directional Flash bus cycles read/write data 32 t bp Byte program time in integer 0 < t bp < 2 cen out Chip enable low system clock cycles 32 oen out Transmit data low t se Sector erase time in integer 0 < t se < 2 system clock cycles wen out Transmit data valid low 32 t ce Chip erase time in integer 0 < t ce < 2 system clock cycles 32 General Description t aa Address access time integer 0 < t aa < 2 in system clock cycles dw Flash data width integer 8 or 16 FLASH CONT is a JEDEC compliant Flash controller IP Core that provides a convenient way of interfacing your FPGA or ASIC to an depth Flash command FIFO integer 2 external FLASH memory component. The IP Core features a simple-to depth use command interface and is fully synchronous with the system clock. log2d Flash command FIFO integer log2 depth log2 (depth) The Flash controller is comprised of two main blocks as described by Figure 1. These blocks are the command FIFO and the main controller state machine that generates the correct signalling to the Flash memory. Copyright 2015 www.zipcores.com Download this VHDL Core Page 1 of 5FLASH CONT Parallel FLASH Memory Controller Rev. 1.1 The command FIFO uses the standard Zipcores valid-ready streaming Figures 3, 4, 5 and 6 on the following pages show the timing waveforms protocol. This is a synchronous interface in which commands, addresses with the physical Flash component. These waveforms and pinouts follow and data are written to the FIFO on the rising-edge of clk when flash val the standard JEDEC specification for Flash EEPROM devices. All timing 1 and flash rdy are both high . parameters shown can be configured using the generic IP Core settings. The command FIFO may be used to queue up a sequence of commands to the Flash memory, and in doing so, can help to alleviate the speed differences between the system and the Flash device. The depth of the command FIFO may be configured with the generic parameters depth and log2d. Increasing the depth of the FIFO will allow more commands to be queued up. The 2-bit flash cmd signal is decoded as follows: 00 : Write byte command 01 : Sector erase command 10 : Chip erase command 11 : Byte read command The output ports to the Flash use a standard JEDEC pinout for an 8 or 16-bit EEPROM device. These pins may be connected directly to the external Flash memory component. The controller is compatible with most standard COTS devices such as those from Microchip, Atmel, AMD, Winbond, EON and STmicroelectronics. Functional Timing Figure 2 shows the user interface with Flash controller IP Core. The flash cmd, flash addr and flash data signals are sampled on the rising edge of the system clk when flash val and flash rdy are both high. If the flash rdy signal is low then this indicates that the command FIFO is full and no further commands should be sent until the FIFO has emptied. Read data from the Flash controller appears on the rdata port with rdata val signifying valid data. Read data is also synchronous with the system clock. Figure 2: Flash controller user-interface timing Figure 3: Write byte timing sequence 1 See Zipcores application note: app note zc001.pdf for more examples of the valid-ready streaming protocol. Copyright 2015 www.zipcores.com Download this VHDL Core Page 2 of 5