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SIN X 16-bit Sine Function Rev. 1.2 Key Design Features Block Diagram Synthesizable, technology independent VHDL Core Function y = sin(x) Input range 0 x /2 (Quarter wave) Output range 0 y 1 Based on a quadratic polynomial with dynamic coefficients Input values as 16-bit unsigned fractions Output values as 16-bit unsigned fractions in radians Accurate to within 0.0002 Figure 1: sin x function architecture High-speed fully pipelined architecture 3 clock-cycle latency General Description Applications SIN X (Figure 1) calculates the sine of an angle. It has a fully pipelined architecture and uses fixed-point mathematics throughout. Input values are accepted as 16-bit unsigned values in the range 0 to /2. Output values are 16-bit unsigned values in the range 0 to 1. For input values Fixed-point mathematics greater than /2, the output saturates to 1.0. Both input and output values are in 16 15 format with 1 integer bit and 15 fraction bits. As an Quadrature signal generation in digital communications example the input value 0xC000 would signify the value 1.5. Alternative to using a 65536 x 16-bit LUT (128kbytes) nd Internally, the function uses a 2 order polynomial of the form: Pin-out Description 2 y=ax bxc Pin name I/O Description Active state The coefficients a, b and c dynamically change with respect to the input value in order to generate a more accurate approximation. The output clk in Synchronous clock rising edge result is accurate to within 0.0002. en in Clock enable high Values are sampled on the rising clock-edge of clk when en is high. The x in 15:0 in Input value in radians data function has a 3 clock-cycle latency. y out 15:0 out Output value data Functional Timing Functional Specification Figure 2 demonstrates the computation of y = sin(x), where x = 0x37E4 (0.4366 as a decimal fraction). The result, 0x3621 (0.4229 in decimal) Value Type Valid range has a latency of 3 clock cycles. x in 15:0 16-bit unsigned fraction in 16 15 format 0, /2 y out 15:0 16-bit unsigned fraction in 16 15 format 0, 1 Accuracy to within 0.0002 Figure 2: Calculation of y = sin(x) Copyright 2012 www.zipcores.com Download this VHDL Core Page 1 of 2SIN X 16-bit Sine Function Rev. 1.2 Source File Description Synthesis All source files are provided as text files coded in VHDL. The following The source file sin x.vhd is the only file required for synthesis. There are table gives a brief description of each file. no sub-modules in the design. The VHDL core is designed to be technology independent. However, as a benchmark, synthesis results have been provided for the Xilinx Virtex 6 Source file Description and Spartan 6 FPGA devices. Synthesis results for other FPGAs and sin x.vhd Top-level block technologies can be provided on request. sin x bench.vhd Top-level test bench Resource usage is specified after Place and Route. Functional Testing VIRTEX 6 Resource type Quantity used Slice register 40 An example VHDL testbench is provided for use in a suitable VHDL simulator. The compilation order of the source code is as follows: Slice LUT 54 Block RAM 0 1. sin x.vhd DSP48 3 2. sin x bench.vhd Occupied slices 20 Clock frequency (approx) 300 MHz The simulation must be run for at least 1 ms during which time a 16-bit input stimulus in the range 0 to 65535 will be generated. The test terminates automatically. SPARTAN 6 The simulation generates a text file called sin x out.txt. This file contains Resource type Quantity used the output results captured during the test. The results of the test are shown graphically in Figure 3 below: Slice register 40 Slice LUT 52 Block RAM 0 DSP48 3 Occupied slices 25 Clock frequency (approx) 200 MHz Revision History Revision Change description Date 1.0 Initial revision 28/04/2008 1.1 Improved accuracy and updated synthesis 07/04/2009 results 1.2 Updated synthesis results for Xilinx 6 06/06/2012 series FPGAs Figure 3: Plot of test results for sin x function Copyright 2012 www.zipcores.com Download this VHDL Core Page 2 of 2