IEEE TO FIXED 32-bit floating-point to fixed-point converter Rev. 1.1 Key Design Features Block Diagram Synthesizable, technology independent VHDL Core 32-bit floating-point input Signed fixed-point or integer output Configurable word and fraction width up to 32 integer bits and 23 fraction bits IEEE 754 compliant High-speed fully pipelined architecture 2 clock-cycle latency Applications Figure 1: 32-bit Floating-point to Fixed-point Floating-point pipelines and arithmetic units converter Floating-point processors General Description Interfacing between floating-point and fixed-point number systems IEEE TO FIXED (Figure 1) is a high-speed fully pipelined conversion unit that accepts a 32-bit bit floating-point number as input and generates a Pin-out Description fixed-point representation at the output. The input number is based on the IEEE 754 standard with the bits arranged in the following format: Pin name I/O Description Active state clk in Synchronous clock rising edge en in Clock enable high ieee in 31:0 in Floating-point input in IEEE data 754 format fixed out dw - 1:0 out Signed fixed-point or data The real number representation of the floating-point number may be integer output in dw fw calculated as: format ofl out Overflow flag high E127 Value=1S2 1.M inf out Infinity flag high den out Denormalized number flag high The fixed-point format is configured using the generic parameters dw and nan out NaN flag high fw. The value dw specifies the width of the output word and fw specifies the number of fraction bits. Generic Parameters The output may be specified as either a signed fixed-point number or a signed integer. If a signed integer is preferred, then fw must be set to 0. In all cases dw must be at least 2 bits and fw must be less than dw. Generic name Description Type Valid range As an example, to generate a 12-bit fixed-point output with 8 fraction bits dw Fixed-point word integer 2 dw 32 the generic parameters must be set to: dw = 12, fw = 8. In this example width the output word would be arranged as follows: fw Fixed-point integer 0 fw 23 fraction width (fw < dw) Copyright 2011 www.zipcores.com Download this VHDL Core Page 1 of 3IEEE TO FIXED 32-bit floating-point to fixed-point converter Rev. 1.1 Alternatively, consider the case where the output format is an 8-bit signed integer. Setting dw = 8 and fw = 0, the output word would be: In addition, there are some special cases that need to be observed. In the case of a positive floating-point input being larger than the maximum representable fixed-point number then the output will saturate to the maximum positive fixed-point number. Likewise, the output will saturate to the maximum allowable negative number if the a negative floating-point input is too large. In both instances of positive and negative overflow, the Figure 3: Floating-point to 12 8 fixed-point with flags signal ofl will be asserted with the output value. If the input floating-point value is a denormalized number, then the fixed- Source File Description point output will be 0 and the den flag will be asserted high. If the input is a NaN then the fixed-point output will be set to 0 and the nan flag asserted. Finally, the case of the input being positive or negative Infinity All source files are provided as text files coded in VHDL. The following is treated in the same manner as a positive or negative overflow, with table gives a brief description of each file. additional inf flag also being asserted. All values are sampled on the rising clock-edge of clk when en is high. The function has a 2 clock-cycle latency. Source file Description ieee to fixed.vhd Top-level component Functional Timing ieee to fixed bench.vhd Top-level test bench Figure 2 demonstrates the conversion of two floating-point numbers. The Functional Testing first number is 0xC0FE6666 and the second is 0x40F80000 which represent the real numbers -7.95 and 7.75 respectively. The generic parameters have been set to: dw = 12, fw = 8. The results are available An example VHDL testbench is provided for use in a suitable VHDL two clock cycles later. simulator. The compilation order of the source code is as follows: 1. ieee to fixed.vhd 2. ieee to fixed bench.vhd The VHDL testbench instantiates the top-level component and the user may modify the generic parameters dw and fw as required The simulation must be run for at least 2 ms during which time the ieee to fixed component will receive an input stimulus of randomized floating-point numbers. The simulation generates two text files called: ieee to fixed in.txt and ieee to fixed out.txt. These files respectively contain the input and output values captured during the test. Figure 2: Floating-point to 12 8 fixed-point conversion Synthesis Figure 3 shows a sequence of floating-point exceptions that cause the The source file ieee to fixed.vhd is the only file required for synthesis. various flags to be exercised. The first value of 0xC101999A represents There are no sub-modules in the design. the number -8.1. The largest negative number allowed in 12 8 format is -8 so this causes the overflow flag to be asserted. The next three values The VHDL core is designed to be technology independent. However, as represent a denormalized number, +Infinity and NaN. a benchmark, synthesis results have been provided for the Xilinx Virtex 5 and the Altera Stratix III series of FPGA devices. The lowest and highest speed grade devices have been chosen in both cases for comparison. Trial synthesis results are shown with the generic parameters set to: dw = 32, fw = 23. Resource usage is specified after Place and Route. Copyright 2011 www.zipcores.com Download this VHDL Core Page 2 of 3