IIR SOS IIR filter Second-Order-Section Rev. 1.2 Key Design Features Block Diagram Synthesizable, technology independent VHDL Core Fully pipelined architecture for highest possible sample rates 16-bit signed input and output samples 16-bit fixed-point coefficients and scaling factor Internal overflow detection SOS coefficient matrix maps directly to filter coefficients Figure 1: IIR filter SOS (Simplified) Cascade SOS blocks in series for higher-order filters Small implementation size - requiring only 6 H/W multipliers General Description nd IIR SOS is a 2 order IIR filter sometimes referred to as a bi-quad . Applications Internally, it has a fully pipelined architecture permitting the highest possible sample rates for IIR filtering. The IIR block is modular and any number of SOS blocks may be joined in series to implement higher order General purpose Iow-pass, band-pass and high-pass filters filters. Mathematically, the filter implements the difference equation: Specialist filters including: peaking, notching, all-pass, group delay equalization, arbitrary magnitude etc. y n = s b x n b x n1 b x n2 0 0 1 2 IIR filtering in higher sample-rate applications a y n1 a y n2 1 2 High performance filtering when resources are limited In the above equation, the input signal is x n , the output signal is y n and b0, b1, b2, a1, a2 represent the filter coefficients. The value s0 is a scale Pin-out Description factor that is often required in stable IIR implementations to prevent the filter oscillating. Filter coefficients are 16-bits wide and defined as signed fixed-point Pin name I/O Description Active state numbers in 16 13 format - i.e. 1 sign-bit, 2 integer bits and 13 faction clk in Sampling clock rising edge bits. The scale factor is also specified in the same format. The diagram below shows this pictorially: reset in Asynchronous reset low en in Clock enable high coeff s0 15:0 in 16-bit Scale factor in data signed 16 13 format coeff b0 15:0 in Coefficient b0 in signed data 16 13 format coeff b1 15:0 in Coefficient b1 in signed data Input and output samples are signed 16-bit values (their format is purely 16 13 format relative). During normal operation of the filter, if the output samples are coeff b2 15:0 in Coefficient b2 in signed data too large to be accommodated within a 16-bit signed number, then the 16 13 format overflow flag will be asserted and the output samples will saturate to the largest positive or negative value. These are respectively 32767 and coeff a1 15:0 in Coefficient a1 in signed data -32768. 16 13 format Generally, if an overflow occurs, then it indicates an unstable set of filter coeff a2 15:0 in Coefficient a2 in signed data coefficients that have caused the filter to oscillate. Alternatively, small 16 13 format overflows may be prevented by adjusting the input gain to the filter. x in 15:0 in Filter input samples as a data 16-bit signed number Values are sampled on the rising clock-edge of clk when en is high. The latency of the IIR filter between the first input sample and the first output y out 15:0 out Filter output samples as a data sample is 7 clock cycles. Note that it is recommended that before normal 16-bit signed number operation begins, the filter should be reset by asserting the reset signal overflow out Output overflow flag high low for at least one clock cycle. This ensures that the feedback paths of the filter are initialized to zero. Copyright 2012 www.zipcores.com Download this VHDL Core Page 1 of 3IIR SOS IIR filter Second-Order-Section Rev. 1.2 The simulation generates a text file called: iir sos out.txt . This file Functional Timing contains the output samples captured during the course of the test. Figure 4 shows the magnitude, impulse and step response outputs of the nd low-pass Butterworth example. Figure 2 shows a sequence of input samples for the IIR 2 order section Output samples appear 7 clock cycles later. Figure 2: IIR SOS filter input/output samples Figure 3 demonstrates an example of a positive overflow condition where the output sample saturates to the maximum positive number (0x7FFF) for a signed 16-bit value. Figure 3: IIR filter positive overflow and output saturation Source File Description All source files are provided as text files coded in VHDL. The following table gives a brief description of each file. Source file Description iir sos.vhd Top-level block iir sos bench.vhd Top-level test bench Functional Testing An example VHDL testbench is provided for use in a suitable VHDL simulator. The compilation order of the source code is as follows: 1. iir sos.vhd 2. iir sos bench.vhd The VHDL testbench instantiates the IIR SOS filter component. The user may modify the coefficients as required in order to implement the desired nd filter response. The test provided is configured for a 2 order low-pass Butterworth filter with a sample rate of 100MHz. Coefficients for a high- pass Chebyshev, a band-pass Butterworth and an all-pass arbitrary group-delay filter are also provided as examples. Figure 4: 2nd-order low-pass Butterworth filter responses The simulation must be run for at least 100 us during which time the impulse response and step response of the filter is tested. Copyright 2012 www.zipcores.com Download this VHDL Core Page 2 of 3