SPI SLAVE SPI Slave Serial Interface Controller Rev. 1.3 Key Design Features Block Diagram Synthesizable, technology independent IP Core for FPGA, address reg ASIC and SoC CONFIG reset REGISTERS (Read/write) Supplied as human readable VHDL (or Verilog) source code Address reg Config reg n (256 max) TM SPI serial-bus compliant (including Motorola and TI modes) PAD 8 Simple programming makes use of a single control register and sclk a single address register 8 Config reg 2 config reg PAD Architecture allows sustained 8-bit read/write operations Config reg 1 8 ss Config reg 0 SPI SLAVE User-defined number of 8-bit read-write configuration registers CONTROLLER PAD and 8-bit read-only status registers (up to 256 of each type) READ Status reg n (256 max) MUX mosi User-defined preset default values for all configuration registers oe PAD Configurable clock polarity setting (CPOL) 8 sel Status reg 2 status reg miso Configurable clock phase setting (CPHA) Status reg 1 clk Control reg Status reg 0 SPI bus signals are treated asynchronously in relation to the STATUS system clock REGISTERS (Read only) flags control reg Support of system clock to SPI clock ratios of 6:1 (or higher) 1 Typical data rates of 50 Mbps+ on basic FPGA devices Figure 1: SPI Slave Interface Controller architecture Applications Pin-out Description SPI slave communications Pin name I/O Description Active state Inter-chip board-level communications clk in Synchronous clock rising edge Robust communication at higher data rates than other serial reset in Asynchronous reset low protocols such as I2C, UART and USB 1.X TM sclk in SPI Serial clock rising or falling 2 edge TM Generic Parameters ss in SPI Serial select low TM mosi in SPI data Master out / Slave in Generic name Description Type Valid range TM miso tristate SPI data num config Number of integer 2 regs 256 out Master in / Slave out Configuration registers (power of 2) co flag out Control register write pulse high num config log2 Log2 number of integer Log2 Configuration registers (num config) ad flag out Address register write pulse high num status Number of integer 2 regs 256 wr flag out Config register write pulse high Status registers (power of 2) rd flag out Config register read pulse high num status log2 Log2 number of integer Log2 ro flag out Status register read pulse high Status registers (num status) control reg 7:0 out Internal control register data cpol Clock polarity integer 0, 1 address reg 7:0 out Internal address register data cpha Clock phase integer 0, 1 config reg out Configuration register data num config*8-1:0 output bits status reg in External status register data num status*8-1:0 input bits 1 Maximum attainable data rate will be determined by the choice of 2 Note that the serial clock characteristics are dependent on the CPOL TM device and the and the physical characteristics of the bus and CPHA settings. See the SPI specification for more details Copyright 2021 www.zipcores.com Download this IP Core Page 1 of 5SPI SLAVE SPI Slave Serial Interface Controller Rev. 1.3 configuration register or a status register is to be accessed. The INC flag General Description (when set) turns off the address pointer auto-increment function. Bits U4 to U0 are user defined flags that may be programmed as required. The TM address register contains the address of the first register to be accessed The SPI SLAVE IP Core is an SPI compliant slave interface controller. in the chosen register bank. Once the control and address registers have The controller decodes the bus signals and de-serializes them into a been written, the next 8 serial clocks are used to synchronize a write to a series of 8-bit bytes. Communication with the slave controller is achieved configuration register or a read from a configuration/status register. by programming a single control register and a single address register. The control register defines whether the transfer is a read or write and Normally after each 8-bit read or write, the internal address register is also the type of register to be accessed (config or status). The address incremented by 1 and the master may write or read a further 8-bits. This register provides an index into the chosen register bank. means that successive back-to-back reads or writes will be performed on the next register in the chosen register bank. Once the maximum Both the config registers and the status registers are directly connected to address has been reached, the address pointer will wrap around back to the external ports of the controller. The config registers provide general 0. Note that the address auto-increment function may be disabled by purpose read/write bits for the control of an external device. The status setting the INC flag in the control register to 1 . registers are read only and allow the state of external pins to be monitored via the SPI interface. Any number of sequential register read or write operations may be performed (to the same register bank). The SPI bus transfer will All inputs to the slave interface controller are driven by the bus Master terminate immediately as soon as ss is driven high. If the user wishes to with the exception of miso which is a tristate output. The signal miso is read and write different register banks, the current SPI transfer must be normally in the high-impedance state unless a read operation is in active terminated before the next bank is accessed. progress. The SPI slave controller is comprised of three main blocks as described by Figure 1. These blocks are the SPI Slave Controller core, The controller state machine generates a series of output flags whenever the Configuration register bank and the Status register bank. an 8-bit read or write to one of the internal registers is performed. These flags take the form of a single pulse that lasts for one system clock cycle. The strobes may be used as interrupt or valid flags to indicate that the SPI Slave Controller Core contents of one of the registers has changed. The slave controller core is a state-machine that continually monitors the Clock Polarity and Phase settings state of the SPI signals. An SPI transfer begins with the high-to-low transition of the slave select signal ss. Once ss is driven low, the controller will sample the next 16-bits from the master at the mosi input. The generic settings cpol and cpha determine how the serial data is Bits are sampled on either the rising or falling edge of sclk depending on sampled and changed with respect to the serial clock. These settings are the clock configuration settings cpol and cpha. TM defined in the standard SPI specification. The table below shows a brief summary of these settings. The first 8-bits in the transfer are written to the internal control register and the next 8-bits are written to the internal address register. Figure 2 shows the programming of the control and address registers in more CPOL CPHA Description detail. 0 0 Serial clock default state logic 0 Data sampled on rising-edge of serial clock Data changed on falling-edge of serial clock CONTROL REGISTER 0 1 Serial clock default state logic 0 7 6 5 4 3 2 1 0 Data sampled on falling-edge of serial clock Data changed on rising-edge of serial clock U4 U3 U2 U1 U0 INC C/S R/W 1 0 Serial clock default state logic 1 MSB LSB Data sampled on falling-edge of serial clock Data changed on rising-edge of serial clock Bit 0 - Read/Write flag 0 = Write, 1 = Read 1 1 Serial clock default state logic 1 Bit 1 - Config/Status register select 0 = Config, 1 = Status Data sampled on rising-edge of serial clock Data changed on falling-edge of serial clock Bit 2 - Address auto-increment 0 = Auto, 1 = No auto Bit 7:3 - User defined control flags Configuration Register bank ADDRESS REGISTER 7 6 5 4 3 2 1 0 The configuration registers are organized as a bank of 8-bit general purpose read/write registers that may be accessed via the SPI slave A7 A6 A5 A4 A3 A2 A1 A0 interface. The config registers are designed to be used for the general configuration of devices external to the controller. MSB LSB The contents of these registers are made available at the output port Bit 7:0 - Address of register to access config reg. This port contains the contents of all the config register bits concatenated together. This means that bits 7..0 represent the contents of config reg 0, bits 15..8 the contents of config reg 1 etc. Figure 2: Control and Address register definitions The total number of config registers is defined by the generic parameter num config. The total number of configuration registers must be a power Every SPI transfer must begin with a write to the control register and the of 2 for the register addressing to work correctly. All config regsiters may address register. The R/W flag in the control register determines whether be given a user-defined default value which is present after system reset. the operation is a read or a write. The C/S flag determines whether a Copyright 2021 www.zipcores.com Download this IP Core Page 2 of 5