VID OVERLAY Digital Video Overlay Module Rev. 1.5 Key Design Features Block Diagram Synthesizable, technology independent VHDL IP Core Video overlays on 24-bit RGB or YCbCr 4:4:4 video 16 16 Supports all video resolutions up to 2 x 2 pixels Supports any number of input video streams or video overlays (by cascading modules together in series) Programmable video-overlay position and size Per pixel 8-bit alpha transparency Choice of ROP commands including AND, OR and XOR Simple input and output interfaces No complex programming required Easily integrates with all Zipcores Video IP Small implementation size 1 Supports FPGA clock rates in excess of 250 MHz Applications Digital TV and home-media solutions Figure 1: Digital Video Overlay architecture Broadcast TV and film production Pin-out Description Digital-video special effects Multiple video windows Pin name I/O Description Active state clk in Synchronous clock rising edge Animated video windows reset in Asynchronous reset low Picture-in-Picture (PiP) applications vid over en in Enable/disable video high overlay Instrumentation and monitoring (When disabled, the background video passes Network and Tactical operations centres though unchanged) vid rop 1:0 in Raster Operation data CCTV and security camera systems (Performs bitwise operation between background video and overlay video) 0: NOP, 1: AND, 2: OR, 3: XOR vid top x 15:0 in Top-left x position of data video-overlay vid top y 15:0 in Top-left y-position of data video-overlay pixels per line in Number of pixels per line in data 15:0 the overlay video lines per frame in Number of lines per frame data 15:0 in the overlay video 1 Xilinx Virtex 6 FPGA used as a benchmark Copyright 2014 www.zipcores.com Download this VHDL Core Page 1 of 6VID OVERLAY Digital Video Overlay Module Rev. 1.5 In addition, the overlay module supports a number of blending operations Pin-out Description cont ... including an 8-bit alpha channel and bitwise AND, OR and XOR functions. Figure 1 shows the architecture of the digital video overlay module in more detail. Pin name I/O Description Active state pixin0 23:0 in 24-bit RGB source pixel in data Input Frame Sync units (background video) pixin0 vsync in Vertical sync in high (Coincident with first pixel Input pixels for both the background video (pixin0) and the overlay video of frame) (pixin1) enter via two separate frame sync modules. The purpose of each module is to find the first vsync of both streams in order synchronize the pixin0 hsync in Horizontal sync in high output frame correctly. If the vsync of the background video is found first, (Coincident with first pixel then further pixels in the background image are held off until the the of line) corresponding vsync in the overlay stream is found. Likewise, if the pixin0 val in Input pixel valid high overlay vsync is found first then further overlay pixels are held off until the background vsync is found. Once both vsyncs are found then normal pixin0 rdy out Ready to accept input pixel high operation begins with the background video stream controlling the flow of (handshake signal) pixels into the module. pixin1 23:0 in 24-bit RGB source pixel in data If at any point a system reset occurs, then the module will resynchronize (overlay video) to the next start of frame for both the background and overlay streams pixin1 alpha 7:0 in Overlay pixel transparency data before normal operation continues. 0: Fully transparent 1: Fully opaque Input Video Multiplexer pixin1 vsync in Vertical sync in high (Coincident with first pixel of frame) The video multiplexer is responsible for controlling the flow of pixels into pixin1 hsync in Horizontal sync in high the video overlay module. It s main function is to detect whether the (Coincident with first pixel current pixel to be displayed lies within the overlay region defined by the of line) parameters vid top x, vid top y, pixels per line and lines per frame. If the current pixel lies outside the overlay region, the input pixel from the pixin1 val in Input pixel valid high background video passes though unchanged. If the pixel lies inside the overlay region, then pixels are processed in the pixel blending unit. pixin1 rdy out Ready to accept input pixel high (handshake signal) The video overlay position and size may be updated as and when pixout 23:0 out 24-bit RGB output pixel data required. If these parameters are not static, then it is desirable that these parameters be updated simultaneously and once per frame. To be extra pixout vsync out Vertical sync out high sure the reset signal maybe toggled for at least one clock cycle after pixout hsync out Horizontal sync out high changing parameters. This will flush all pixels from the pipeline and cause the input streams to re-sync. pixout val out Output pixel valid high Figure 2 shows the relationship between the background video display pixout rdy in Ready to accept output high area and the defined video overlay window. It is important that the pixel overlay parameters exactly match the size of the video overlay. In addition, the whole video overlay window must lie within the dimensions of the background video - otherwise image corruption will result. General Description VID OVERLAY is a highly versatile video multiplexer that allows one video stream to be inserted over another. By cascading a series of video overlay modules together, any number of video sources may be multiplexed together. The module supports input video streams of any 16 16 resolution or aspect ratio up to 2 x 2 pixels in size. Video overlay parameters may be changed on a frame-by-frame basis to dynamically change the size and position of the video overlay. Pixels and syncs flow in and out of the video overlay module in accordance with the valid-ready pipeline protocol. Pixels and syncs are sampled at the module inputs on a rising clock-edge when val is high and rdy is high. Likewise, pixels and syncs are transferred out of the module on a rising clock-edge when val is high and rdy is high. The pipeline protocol allows both input and output interfaces to be stalled independently. The dimensions of the output video are controlled entirely by the background video stream (pixin0) . This means that if the source video input at stream 0 is 1024x768 pixels then the output video will also be 1024x768 pixels in resolution. The video overlay enters the module via stream 1 and must be smaller or equal in size to the background video Figure 2: Video overlay window positioning and size stream. Copyright 2014 www.zipcores.com Download this VHDL Core Page 2 of 6