DEINTERLACER Multi-format Video Deinterlacer Rev. 1.3 Key Design Features Block Diagram Synthesizable, technology independent IP Core for FPGA and ASIC reset deint mode Supplied as human readable VHDL (or Verilog) source code 24-bit RGB video support with option for YCbCr video formats if (RGB) (RGB) BOB required pixin pixout ELA 24 24 LCI pixin field pixout vsync Generates clean and progressive video output without combing LINE pixin vsync pixout hsync or tearing BUFFER pixin hsync pixout val NxN Reduced softening and sawtooth artefacts FILTER pixin val Supports three different de-interlacing modes including: pixin rdy Interpolated BOB, ELA (Edge-based Line-Average) and a frame rate customized version of LCI (Low-Complexity Interpolation) pixels per line 12 line width Supports all interlaced video formats up to 4096 x 4096 pixels MULTI-FORMAT lines per field 12 VIDEO DEINTERLACER log2 line width in resolution. Examples include: 480i, 576i, 1080i etc. field polarity clk Output is one frame per interlaced field Fully pipelined architecture with simple flow-control No frame buffer required Figure 1: Video deinterlacer architecture Supports 200MHz+ operation on basic FPGA devices Pin-out Description Applications Pin name I/O Description Active state High-quality video de-interlacing without the overhead of a frame buffer clk in Synchronous clock rising edge Conversion of legacy SDTV formats to HDTV video formats reset in Asynchronous reset low pixels per line in Number of pixels per input data Generating progressive RGB video via inexpensive PAL/NTSC 11:0 line decoder chips lines per field in Number of lines per field data Digital TV set-top boxes and home media solutions 11:0 pixin 23:0 in 24-bit RGB pixel in data Generic Parameters pixin field in Input field number data pixin vsync in Vertical sync in high (Coincident with first pixel Generic name Description Type Valid range of a new input field) deint mode De-interlacing mode integer 0: BOB pixin hsync in Horizontal sync in high 1: ELA (Coincident with first pixel 2: LCI of a new input line) 3: MIX (option) pixin val in Input pixel valid high frame rate Output frame rate integer 0: min 1: max pixin rdy out Ready to accept input pixel high 4 12 (handshake signal) line width Width of linestores in integer 2 < pixels < 2 pixels pixout 23:0 out 24-bit pixel out data log2 line width Log2 of linestore width integer log2(line width) pixout vsync out Vertical sync out high (Coincident with first pixel field polarity Polarity of the std logic 0: even field of a new output frame) pixin field input when signified by 0 the field is even pixout hsync out Horizontal sync out high 1: even field (Coincident with first pixel signified by 1 of a new output line) pixout val out Output pixel valid high Copyright 2016 www.zipcores.com Download this VHDL Core Page 1 of 6DEINTERLACER Multi-format Video Deinterlacer Rev. 1.3 In addition, the input interface uses the handshake signal pixin rdy. General Description When the module asserts pixin rdy low, then all input signals must be stalled until pixin rdy is asserted high again. On the output side, pixels and syncs are valid when pixout val is asserted high. The DEINTERLACER IP Core is a high quality 24-bit RGB video deinterlacer capable of generating progressive output video at up to On receipt of the first valid vsync after reset, the deinterlacing operation 4096x4096 pixels in resolution. The design is fully customizable, begins and output lines are generated in accordance with the chosen filter supporting any desired interlaced video format. algorithm. The deinterlacer will generate two output lines for every input line while the input field is active. Due to the uneven ratio of input to The deinterlacer allows for three possible filter algorithms - either BOB, output lines then, on average, pixin rdy will have a 50% duty cycle. In ELA or LCI. All three methods are intra-field methods that perform order to maintain maximum pixel throughput without stalling, the spatial filtering within the same field. For this reason, the output video is deinterlacer should be clocked at at least double the input pixel rate. A not subject to combing or tearing which is characteristic of a traditional typical arrangement is shown in Figure 2 below: weave approach. Each algorithm has it relative merits in terms of image quality and hardware complexity. In particular, the enhanced LCI algorithm provides ASYNC FIFO excellent all-round performance with reduced image softening and crisp clean edges. pixels in pixels out Pixels flow into the module in accordance with the valid-ready pipeline DEINTER- protocol. The pixel, sync flags and field number are transferred into the LACER deinterlacer on a rising clock-edge when pixin val and pixin rdy are both active high. At the output interface, pixels and syncs are valid on a rising clock-edge when pixout val is high. clk > 2 x clk The basic architecture of the deinterlacer is shown in Figure 1. Input lines are buffered and organised spatially before being filtered according to the chosen algorithm. Each input field is converted to a single output frame with twice the number of lines per field. Figure 2: Deinterlacer clocking arrangement for maximum efficiency Output Frame rate Deinterlacing filter algorithm When the generic parameter frame rate is set to 1 then the output frame The generic parameter deint mode selects one of three possible rate is equal to the input field rate. When set to 0 , the output frame rate deinterlacing filter algorithms. These are BOB, ELA or LCI. The choice of is half the field rate. For example, consider an interlaced video input at 50 fields/s. When the frame rate is set to 1 then the output video will be algorithm will determine the quality of the resulting output video as well as the size and complexity of the hardware implementation. The following generated at 50 frames/s. Conversely, when the frame rate is set to 0 , table outlines the basic characteristics of each method. For empirical test then output video will be generated at 25 frames/s. results for each mode, please refer to the performance section of this document. At half the frame rate, only the even field will generate a complete output frame, and the odd field will be discarded. The polarity of the even field is controlled by the generic parameter frame polarity. Deint mode Description and properties 0: BOB Traditional bob approach. Bilinear interpolation is used Pixels per line and lines per field between adjacent lines to give a smooth graduated image. Method works very well with natural images. Sawtooth artifacts may be present if the image contains The input signals pixels per line and lines per field define the format of sharp lines and edges. Tends to soften image slightly. the interlaced video input. As an example, these values would be set as 720 and 240 if the input video format was digitized NTSC at 720x480 Results in a very small and fast hardware resolution (480i). These values may be modified during normal operation implementation suitable for lower-end applications. of the deinterlacer. Any changes must be followed by a system reset. 1: ELA This method uses a filter window to determine edge- The width of the linestores must be sufficient to hold a complete line of vectors within a 3x3 block. Interpolation is performed interlaced video. The width should be set to the nearest power of 2. For according to the calculated vectors. Generates crisp example, if pixels per line is set to 720 , then line width should be set to and sharp output video. Some minor pixel 1024 and log2 line width should be set to 10 . displacements may be evident when edges are estimated incorrectly. Flow control Results in a medium hardware implementation size. 2: LCI Most complex algorithm. Uses a 5x5 filter window and Pixels flow into the deinterlacer in accordance with the valid-ready calculates more edge-vectors than ELA. Interpolation is 1 pipeline protocol . At the input interface, the signal pixin hsync is performed in more directions and with more pixels. coincident with the first pixel of a new line. The signals pixin vsync and Offers balanced contrast without too much softening. pixin field are coincident with the first pixel of a new field. All input Overall video quality is consistently better than BOB or signals are qualified by the pixin val signal being asserted high. ELA. Results in the largest hardware implementation size. 1 See Zipcores application note: app note zc001.pdf for more examples of how to use the valid-ready pipeline protocol Copyright 2016 www.zipcores.com Download this VHDL Core Page 2 of 6