pixout pixout vsync pixout hsync pixout val pixout rdy DEINTERLACER MA Motion-adaptive Video Deinterlacer Rev. 1.4 Key Design Features Block Diagram Synthesizable, technology independent IP Core for FPGA, ASIC and SoC Supplied as human readable VHDL (or Verilog) source code 24 Fully asynchronous 24-bit RGB video inputs (Option to support YCbCr video formats if required) 24-bit RGB video outputs synchronized to the system clock reset Generates clean and progressive output video without combing VIDEO or tearing clk FRAME err ovfl1 BUFFER Excellent vertical resolution and much better than intra-line err ovfl2 deint mode interpolation methods line width Supports three different deinterlacing modes including: Classic log2 line width weave, inter-line interpolation and interpolation adapted for motion between fields INPUT LINE field polarity BUFFER Supports all interlaced video formats such as: 480i, 576i, 1080i etc. All modes are real-time programmable mem rw mem start addr0 WEAVE 128 Integrated frame buffer dynamically skips and repeats frames in mem wdata mem start addr1 INTERP order to adapt to the desired input and output frame rates 32 MA mem addr mem burst size MA Diagnostic flags asserted in the event of an input or output mem frame repeat FILTER mem addr val buffer overflow mem addr rdy 16 128 Simple generic memory interface suitable for SDRAM, DDR, pixels per line mem rdata DDR2, DDR3 etc. OUTPUT LINE 16 lines per field BUFFER mem rdata val 32 Fully pipelined architecture with simple flow-control. Compatible words per field with all other Zipcores video IP, AXI4-stream and Avalon-ST MOTION-ADAPTIVE VIDEO DEINTERLACER Supports 200MHz+ operation on basic FPGA platforms 24 Applications Studio-quality video de-interlacing Conversion of legacy SDTV formats to HDTV video formats Generating progressive RGB video via inexpensive PAL/NTSC decoder chips Figure 1: Basic video deinterlacer architecture Digital TV set-top boxes. Industrial imaging. Automotive, home and personal media solutions Generic Parameters cont... Generic Parameters Generic name Description Type Valid range mem start addr0 Start address of integer 0 frame buffer 0 in (128-bit aligned) Generic name Description Type Valid range memory deint mode Deinterlacing mode integer 0: WEAVE mem start addr1 Start address of integer 0 selection 1: INTERP frame buffer 1 in (128-bit aligned) 2: MA memory 4 16 line width Width of linestores in integer 2 < pixels < 2 mem burst size Size of memory integer 2, 4, 8, 16, 32 or pixels read/write burst 64 (in 128-bit words) log2 line width Log2 of linestore width integer log2(line width) mem frame repeat Enable/disable frame boolean True/False field polarity Swaps the polarity of boolean True/False repeat mode the input field Copyright 2017 www.zipcores.com Download this IP Core Page 1 of 9 EVEN pixin clk field pixin val pixin vsync pixin field ODD pixin field (RGB) (RGB)DEINTERLACER MA Motion-adaptive Video Deinterlacer Rev. 1.4 GENERIC 128-BIT MEMORY INTERFACE Pin-out Description Pin name I/O Description Active state mem rw out Memory read / write flag 0: write SYSTEM SIGNALS 1: read Pin name I/O Description Active state mem wdata 127:0 out Memory write data data clk in Synchronous system clock rising edge mem addr 31:0 out Memory read / write data reset in Asynchronous reset low address err ovfl1 out Input overflow error high (128-bit aligned) (signifies insufficient input mem addr val out Memory request valid high memory B/W) mem addr rdy in Ready to accept memory high err ovfl2 out Output overflow error high request (signifies insufficient output (handshake signal) memory B/W) mem rdata 127:0 in Memory read data data pixels per line in Number of pixels per input data mem rata val in Memory read data valid data 15:0 = line lines per field in Number of lines per input data 15:0 field General Description words per field in Number of 128-bit words data 31:0 per field The DEINTERLACER MA IP Core is a studio quality 24-bit RGB video Calculated as deinterlacer capable of generating progressive output video at any (pixels per line * 16 16 resolution up to 2 x 2 pixels. The design is fully programmable and lines per field * 24) /128 supports any desired interlaced video format. (Must be a whole number) The design allows for three possible deinterlacing schemes. These are: weave, bilinear interpolation or motion-adaptive interpolation. The weave approach applies no filtering and may be useful to obtain a raw ASYNCHRONOUS INPUT VIDEO INTERFACE (INTERLACED) interlaced format for subsequent processing. The other two methods are classed as inter-field interpolation methods as spatial filtering is Pin name I/O Description Active state performed between both odd and even fields to achieve a clean and pixin clk in Input pixel clock rising edge progressive output. The relative merits and disadvantages of each scheme are discussed further into the document. pixin 23:0 in 24-bit RGB pixel in data The deinterlacer core features a fully integrated video frame buffer. This pixin field in Input field number 0: even buffer is completely elastic and will dynamically skip and/or repeat 1: odd frames depending on the input and output frame rates. All frame buffer (Coincident with first pixel management is handled internally with the provision of a simple memory of a new input field) interface for storing odd and even fields off-chip. The memory interface is 1 pixin vsync in Vertical sync in high 128-bits wide and is completely generic . All memory transfers are sequential bursts of N x 128-bit words and may be adapted for connection (Coincident with first pixel to a variety of memory types such as SDRAM, DDR2 or DDR3. of a new input field) The input video interface is asynchronous to the system clock. Input pixin val in Input pixel valid high pixels are sampled on the rising clock-edge of pixin clk with the signals pixin field and pixin vsync identifying the field number and the first pixel of each field. All signals are qualified by pixin val asserted high. SYNCHRONOUS OUTPUT VIDEO INTERFACE (PROGRESSIVE) Pin name I/O Description Active state Output pixels are synchronous with the system clock and are generated in accordance with a simple valid-ready streaming protocol. The output pixout 23:0 out 24-bit RGB pixel out data pixels and sync flags are transferred at the deinterlacer outputs on a rising clock-edge when pixout val and pixout rdy are both active high. If pixout vsync out Vertical sync out high required, the application circuit may assert pixout rdy low to stall the flow of output pixels. (Coincident with first pixel of a new output frame) The basic architecture of the motion-adaptive deinterlacer is shown in pixout hsync out Horizontal sync out high Figure 1. (Coincident with first pixel of a new output line) pixout val out Output pixel valid high pixout rdy in Ready to accept output high pixel 1 Other memory word widths are available on request. We can also (handshake signal) provide physical interfaces with your chosen memory technology. Please contact Zipcores for more information. Copyright 2017 www.zipcores.com Download this IP Core Page 2 of 9