DDC DEC Digital Down Converter with configurable Decimation Filter Rev. 2.1 Key Design Features Block Diagram Synthesizable, technology independent VHDL Core 1 16-bit signed input/output data samples Digital oscillator with > 100 dB SFDR 16 Digital oscillator phase resolution of 2/2 32 Digital oscillator frequency resolution of Fs/2 Integrated FIR decimation filter with configurable decimation N factors from 0 to 2 Highly optimized design requiring only 12 multipliers per decimate-by-2 stage Each decimate-by-2 filter stage has 80 dB of stop-band 2 attenuation 3 Typical FPGA sample rates of up to 250 MHz Applications Digital I/Q Demodulators Compatible with any digital modulation scheme - e.g. QPSK, Figure 1: DDC simplified architecture BPSK, QAM, WiMAX, WCDMA, COFDM etc. Conversion of IF signals to baseband frequencies for Generic Parameters subsequent processing Generic name Description Type Valid range Pin-out Description num stages Number of decimate- integer 0 by-2 stages Pin name I/O Description Active state dithering Enable phase dither boolean TRUE/FALSE clk in Sample clock (F ) rising edge S lutsize 16/12-bit LUT select integer 16 or 12 32 reset in Asynchronous reset low seed Seed for random std logic 0 < seed < 2 number generator vector en in Input clock enable high (rate F ) S en out out Output clock enable high General Description (rate F /N) S phase inc 31:0 in Phase increment as an data DDC DEC (Figure 1) is a complex-valued digital down-converter with a unsigned 32-bit number configurable number of decimation stages. The design is ideal for high (controls osc frequency) sample-rate applications and permits a digital input signal to be mixed- i in 15:0 in Complex input (Real part) data down and re-sampled at a lower data rate. The DDC is suitable for the as 16-bit signed (rate F ) S down-conversion of any digitally modulated signal to baseband an essential step before digital processing. q in 15:0 in Complex input (Imag part) data as 16-bit signed (rate F ) S The DDC features a high-precision 16-bit DDS oscillator for the digital i out 15:0 out Complex output (Real part) data mixing stage. This oscillator is fully programmable and offers excellent as 16-bit signed (rate F /N) phase and frequency resolution. The digital mixing stage is a complex S multiplier that allows the mixing of both real and imaginary (I/Q) inputs. If q out 15:0 out Complex output (Imag part) data only real inputs are required, then the imaginary input (q in) should be as 16-bit signed (rate F /N) S tied low. N The output decimation stage features a configurable decimate-by-2 poly- phase filter for both I and Q channels. Each filter stage is highly optimized to use only 12 multipliers while still achieving 80 dB of stop- 1 Data sample width may be modified on request band attenuation. 2 Filter characteristic may be modified on request 3 Xilinx Virtex 6 FPGA used as a benchmark Copyright 2012 www.zipcores.com Download this VHDL Core Page 1 of 5DDC DEC Digital Down Converter with configurable Decimation Filter Rev. 2.1 The design features two clock-enable signals. The signal en is the global Digital oscillator (DDS) clock-enable and may be used to enable/disable sampling for the whole circuit. The output clock-enable signal en out is only asserted when the decimated output samples are active. For instance, when decimating by The frequency of the DDS output waveform is controlled by the phase a factor of 2, then this signal will have a 50% duty cycle. When increment (phase inc) on a clock-by-clock basis. The phase increment decimating by a factor of 4 it will have a 25% duty cycle and so on. may be calculated using the formula: Complex digital mixer 32 =(F 2 )/ F +0.5 inc out s The digital mixing process performs a complex multiplication between the Fout is the desired oscillator frequency and FS is the system sampling input samples i in and q in and the samples from the internal DDS frequency. Note that the phase increment must be adjusted to the modules. For any given frequency component in the input signal, the nearest integer value. The minimum and maximum frequencies the frequency component of the output signal has two components Fout1 and oscillator can generate are given by the following formulas: Fout2 given by the following relationship: 32 F = F F , F = F + F F = F / 2 , F < F / 2 out1 1 2 out2 1 2 min s max s F is the frequency component of the input signal and F is the oscillator The process of phase quantization introduces noise on the phase signal 1 2 frequency. It can be seen that by choosing a suitable oscillator and it produces unwanted spurious spectral components in the DDS frequency, then the signal of interest may be mixed-down to baseband so output signal (referred to as spurs). The difference between the carrier that the centre frequency is positioned at 0Hz. Normally the higher level and the maximum level of spurs is called the Spurious Free frequency mixer product (Fout2) is unwanted and will be attenuated by the Dynamic Range (SFDR). By setting the generic parameter dithering to decimation filter output stages. true, then the incidence and magnitude of these spurs can be reduced significantly. The dithering function uses a random number generator Figure 2. below shows the basic mixing principal in which a generic input with the starting seed specified in the generic parameter. signal is shifted to baseband using a 20MHz oscillator frequency. Decimation filter The decimation filter allows the output from the mixer to be decimated by any power of 2. Each decimate-by-2 stage has a magnitude response as shown in Figure 3. below. Figure 3: Decimation filter magnitude response for a single decimate-by-2 stage The number of decimate-by-2 stages is specified by the generic parameter num stages. For instance, setting this parameter to 2 will Figure 2: Mix-down of a 4MHz B/W signal to decimate the output samples by a factor of 4. Setting the parameter to 0 baseband. (a) Source signal, (b) Baseband will eliminate all decimation and will output the signals directly from the signal after mixing (decimation filter disabled) digital mixer. Figure 4. demonstrates the result of mixing and decimating a generic 4MHz wideband signal by various stages. Copyright 2012 www.zipcores.com Download this VHDL Core Page 2 of 5