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ATAN X 16-bit Arctan Function Rev. 1.3 Key Design Features Block Diagram Synthesizable, technology independent VHDL Core Function y = atan(x) Input range 0 x 1 Output range 0 y /4 Based on a quadratic polynomial with dynamic coefficients Input values as 16-bit unsigned fractions Output values as 16-bit unsigned fractions in radians Accurate to within 0.00004 radians Figure 1: Atan x function architecture 1 High-speed 250MHz+ operation Fully pipelined architecture General Description 3 clock-cycle latency ATAN X (Figure 1) calculates the inverse tangent of a fraction. It has a fully pipelined architecture and uses fixed-point mathematics throughout. Input values are accepted as 16-bit unsigned fractions in the range 0 to 1. Applications Output values are 16-bit unsigned fractions in the range 0 to /4. Both input and output values are in 16 16 format with 0 integer bits and 16 fraction bits. As an example the input value 0x4000 would signify the Fixed-point mathematics fraction 0.5. Phase measurements in digital communications nd Internally, the function uses a 2 order polynomial of the form: Alternative to using a 64k x 16-bit LUT (128 kbytes) 2 y=ax bxc Pin-out Description The coefficients a, b and c dynamically change with respect to the input value in order to generate a more accurate approximation. The output Pin name I/O Description Active state result is accurate to within 0.00004 radians. clk in Synchronous clock rising edge Values are sampled on the rising clock-edge of clk when en is high. The en in Clock enable high function has a 3 clock-cycle latency. x in 15:0 in Input value data y out 15:0 out Output value in radians data Functional Timing Figure 2 demonstrates the computation of y = atan(x), where x = 0xA673 Functional Specification (0.6502 as a decimal fraction). The result, 0x9395 (0.5765 in decimal) has a latency of 3 clock cycles. Value Type Valid range x in 15:0 16-bit unsigned fraction in 16 16 format 0, 1 y out 15:0 16-bit unsigned fraction in 16 16 format 0, /4 Accuracy to within 0.00004 radians Figure 2: Calculation of y = atan(x) 1 Xilinx Virtex 6 FPGA used as a benchmark Copyright 2012 www.zipcores.com Download this VHDL Core Page 1 of 2ATAN X 16-bit Arctan Function Rev. 1.3 Source File Description Synthesis All source files are provided as text files coded in VHDL. The following The source file atan x.vhd is the only file required for synthesis. There table gives a brief description of each file. are no sub-modules in the design. The VHDL core is designed to be technology independent. However, as a benchmark, synthesis results have been provided for the Xilinx Virtex Source file Description 6 and Spartan 6 FPGA devices. Synthesis results for other FPGAs and atan x.vhd Top-level block technologies can be provided on request. atan x bench.vhd Top-level test bench Resource usage is specified after Place and Route. Functional Testing VIRTEX 6 Resource type Quantity used Slice register 41 An example VHDL testbench is provided for use in a suitable VHDL simulator. The compilation order of the source code is as follows: Slice LUT 50 Block RAM 0 1. atan x.vhd DSP48 3 2. atan x bench.vhd Occupied slices 16 Clock frequency (approx) 270 MHz The simulation must be run for at least 1 ms during which time a 16-bit input stimulus in the range 0 to 65535 will be generated. The test terminates automatically. SPARTAN 6 The simulation generates a text file called atan x out.txt. This file Resource type Quantity used contains the output results captured during the test. The results of the test are shown graphically in Figure 3 below: Register 41 Slice LUT 50 Block RAM 0 DSP48 3 Occupied slices 22 Clock frequency (approx) 200 MHz Revision History Revision Change description Date 1.0 Initial revision 28/04/2008 1.1 Improved accuracy and updated synthesis 07/04/2009 results 1.2 Improved accuracy further and updated 30/04/2009 synthesis results Figure 3: Plot of test results for atan x function 1.3 Updated synthesis results for Xilinx 6 06/06/2012 series FPGAs Copyright 2012 www.zipcores.com Download this VHDL Core Page 2 of 2