SKU102 Zipcores

SONY CAM IF Sony Camera LVDS Interface Rev. 1.1 Key Design Features Block Diagram Synthesizable IP Core for Xilinx FPGA 7-series and later (other FPGA devices and vendors supported on request) bitslip Supplied as human-readable RTL source code CAM TXOUT0 P CAM TXOUT0 N CAM TXOUT1 P 4 x LVDS Compatible with all Sony FCB-EV Series LVDS video CAM TXOUT1 N lanes in cameras such as the FCB-EV7520 and FCB-EV7320 models SMPTE LOCK single CAM TXOUT2 P mode CAM TXOUT2 N 28 16 16 Support for HD1080p60 (double-mode) and HD1080p30 CAM TXOUT3 P BIT or or or (single-mode) operation (other modes supported on request) CAM TXOUT3 N ALIGN SMPTE ISERDES 56 32 32 + 274M 7:1 SMPTE DATA BYTE DEC CAM TXOUT4 P x N Choice of 8 x LVDS data lanes or 4 x LVDS data lanes SMPTE SOF ALIGN CAM TXOUT4 N CAM TXOUT5 P SMPTE SOL 8 x LVDS Generates a standard SMPTE 274M output video stream CAM TXOUT5 N lanes in SMPTE DE CAM TXOUT6 P double CAM TXOUT6 N mode CAM TXOUT7 P Applications CAM TXOUT7 N cam clk ser clk Simple connectivity to the Sony FCB-EV series HD-cameras pix clk (148.5 MHz) (74.25 MHz) SMPTE PCLK cam clk (74.25 MHz) CAM TXCLKOUT P PLL SMPTE TCLK Easily adaptable for other LVDS cameras CAM TXCLKOUT N ser clk (519.75 MHz) SMPTE SCLK Replacement for the Thine THC63LVD series or the Rohm RESET N BU90R series LVDS receiver ICs recommend by Sony Figure 1: Sony LVDS camera interface (internal architecture) Pin-out Description Pin name I/O Description Active state General Description RESET N in Asynchronous reset low CAM TXCLKOUT P in LVDS input clock LVDS The SONY CAM IF IP Core (Figure 1) provides a simple way to connect CAM TXCLKOUT N (74.25 MHz nominal) differential the Sony FCB-EV range of cameras to your FPGA. It serves as a direct replacement for an external LVDS receiver IC and takes advantage of the CAM TXOUT* P in LVDS input data lanes LVDS fast LVDS I/O solutions provided by modern FPGA devices. CAM TXOUT* N (4-lanes single-mode) differential (8-lanes double-mode The interface supports both single-mode and double-mode operation in which 4 x LVDS data lanes or 8 x LVDS data lanes may be connected to SMPTE LOCK out Indicates that receiver high the IP Core. In the standard configuration, the camera input clock has locked to the (TXCLKOUT P/N) is assumed to be set to a frequency of 74.25 MHz. SMPTE video stream This permits operation at HD1080p30 resolution in single-mode (1x16-bit SMPTE PCLK out Pixel clock output synchronous pixels per clock) or HD1080p60 operation in double-mode (2x16-bit pixels 1 (148.5 MHz) clock per clock) . SMPTE TCLK out Camera clock output synchronous The LVDS data lanes are deserialized using the high-speed SERDES (74.25 MHz) clock input resources of the FPGA.. The resulting parallel data are then aligned SMPTE SCLK out Serial clock output synchronous and decoded to provide a standard SMPTE 274M output video stream. (519.75 MHz) clock SMPTE data changes on the rising-clock edge of the SMPTE TCLK (cam clk) signal. SMPTE DATA out Standard SMPTE 274M 16-bit data data stream out (single-mode Other flags are also provided to indicate the presence of active video, the (1080p30 or 1080p60 1 pixel/clock) start of an active frame and the start of an active line. In addition, there is video) a stream locked flag that indicates the bit alignment has succeeded and a 32-bit data valid SMPTE stream has been found. (double-mode 2 pixels/clock) SMPTE SOF out Start of Frame flag high (first pixel active frame) SMPTE SOL out Start of Line flag high (first pixel active line) SMPTE DE out Data Enable flag high (active video is valid) 1 Full details on the camera modes of operation can be found in the Sony FCB-EV series datasheet. Other clocking options and video resolutions may be provided on request. Copyright 2019 www.zipcores.com Download this IP Core Page 1 of 5SONY CAM IF Sony Camera LVDS Interface Rev. 1.1 Data Sampling Considerations Functional Timing The internal clocking is provided by the PLL resources of the FPGA. The The input timing of the LVDS camera interface corresponds exactly to the PLL receives the 74.25 MHz camera LVDS input clock and generates Sony datasheet. For single-mode operation, the Y and C component three further clocks which are are pix clk, cam clk and ser clk. These values are serialized as shown in Figure 3 below. After deserialization, clocks are also made available at the outputs of the IP Core as shown by the output is 1 x 16-bit YcbCr 4:2:2 pixel per clock. Figure 1 above. All three clocks are synchronous with the output SMPTE data stream and the camera clock input. Normally the user will use the cam clk (SMPTE TCLK) output as the SMPTE parallel data is latched on the rising-edge of this clock. The other clocks may also be used by the downstream interface if required. If not, they may be left unconnected in the implementation. One critical thing to take into account when designing with the camera interface is to set the correct phase for the serial clock. The serial clock is the clock used to sample the incoming LVDS bitstream. By modifying the phase of this clock, then the sample point within the data eye is changed. This is shown graphically in Figure 2 below. Ideal sampling point Data eye at FPGA input pads (after LVDS buffer) Figure 3: Sony camera single-mode pixel format The input timing for double-mode is identical save for the fact that 2 x 16- bit pixels are processed and serialized in parallel. The output after deserialization is therefore 2 x 16-bit YcbCr 4:2:2 pixles per clock. Figure 0 4 shows the timing waveforms. 45 90 135 180 225 270 315 Serial clock from PLL with different phase shifts in 45 increments Figure 2: Serial sampling clock relative to the data eye Depending on the physical characteristics of the PCB and the physical properties of the LVDS routing then it may be necessary to modify the phase accordingly. The ultimate goal is to try and position the sample point in the middle of the data eye. To this end, the PLL in the FPGA allows the phase to be shifted by 45 degree steps. By default, the design has an 180 phase shift on the serial clock. This, in principle, should mean the rising-edge appears directly in the middle of the eye. However, some experimentation may be required to achieve the best possible results. Figure 4: Sony camera double-mode pixel format Copyright 2019 www.zipcores.com Download this IP Core Page 2 of 5