SKU12 Zipcores

IEEE MULT 32-bit Floating-point Multiplier IP Core Rev. 1.3 Key Design Features Block Diagram Synthesizable, technology independent IP Core for FPGA, ASIC and SoC v1 Supplied as human readable VHDL (or Verilog) source code 32-bit floating-point arithmetic vout 1 IEEE 754 compliant x High-speed fully pipelined architecture v2 Only 4 clock-cycles of latency VOUT = V1 * V2 en Applications clk Floating-point pipelines and arithmetic units Floating-point processors Figure 1: 32-bit Floating-point Multiplier Pin-out Description General Description Pin name I/O Description Active state The IEEE MULT IP Core (Figure 1) is a high-speed fully pipelined 32-bit bit floating-point multiplier based on the IEEE 754 standard. The clk in Synchronous clock rising edge arrangement of the 32-bit floating-point number is summarized below: en in Clock enable high v1 31:0 in Input operand 1 in IEEE data 754 format MSB LSB Sign Exponent Mantissa v2 31:0 in Input operand 2 in IEEE data (1-bit) (8-bits) (23-bits) 754 format vout 31:0 out Output result in IEEE 754 data format All input and output values comply with the IEEE 754 specification. The real number representation is calculated according to the formula: Functional Specification E127 Value=1S2 1.M Operand v1 Operand v2 Result Standard IEEE Standard IEEE v1 * v2 There are two exceptions to the IEEE 754 specification. The first being that denormalized (subnormal) numbers are treated as zero throughout If v1 * v2 > MaxFloat then result is: the implementation, and the second being that symmetric arithmetic sign(v1) xor sign(v2) Inf rounding is employed (round half-up). If v1 * v2 MinFloat then result is: Other points to note are that NaN is always generated as the value sign(v1) xor sign(v2) 0 0xFFC00000. The maximum floating-point value that may be represented NaN Anything NaN is 0x7F7FFFFF or 0xFF7FFFFF (+/- MaxFloat). Likewise, the minimum floating-point value that may be represented is 0x00800000 or Anything NaN NaN 0x80800000 (+/- MinFloat). This means that a real number lies in the range: +/- Inf +/- 0 NaN +/- 0 +/- Inf NaN 126 127 23 +/- Inf Standard IEEE sign(v1) xor sign (v2) Inf 2 Value 2 22 Standard IEEE +/- Inf sign(v1) xor sign (v2) Inf +/- 0 Standard IEEE sign(v1) xor sign (v2) 0 All values are sampled on the rising clock-edge of clk when en is high. 2 The function has a 4 clock-cycle latency . Standard IEEE +/- 0 sign(v1) xor sign (v2) 0 2 The design may be optimized for higher-speed or lower latency on 1 Some minor features diverge from the IEEE 754 specification request. Please contact Zipcores for more information. Copyright 2018 www.zipcores.com Download this IP Core Page 1 of 2IEEE MULT 32-bit Floating-point Multiplier IP Core Rev. 1.3 XILINX 7-SERIES FPGAS Functional Timing Resource type Artix-7 Kintex-7 Virtex-7 Slice Register 118 118 110 Figure 2 demonstrates the multiplication: 0x40010000 * 0x40407000 = 0x40C0880E (or 2.0010 * 3.0068 = 6.0166 in real numbers). The result Slice LUTs 143 143 139 has a latency of 4 clock cycles. Block RAM 0 0 0 DSP48 4 4 4 1 2 3 4 5 6 7 8 Occupied Slices 60 60 54 clk Clock freq. (approx) 250 MHz 300 MHz 350 MHz en v1 0x40001000 Revision History v2 0x40407000 0x40C0880E vout Revision Change description Date 1.0 Initial revision 30/04/2008 Figure 2: Multiplication of two floating-point numbers 1.1 Updated synthesis results 19/08/2009 Source File Description 1.2 Updated functional specification. Updated 16/09/2011 All source files are provided as text files coded in VHDL. The following synthesis results in line with minor code table gives a brief description of each file. changes 1.3 Cosmetic changes to the source code 02/07/2018 Updated results for Xilinx 7-series Source file Description ieee mult.vhd Top-level component ieee mult bench.vhd Top-level test bench Functional Testing An example VHDL testbench is provided for use in a suitable VHDL simulator. The compilation order of the source code is as follows: 1. ieee mult.vhd 2. ieee mult bench.vhd The simulation must be run for at least 2 ms during which time an input stimulus of randomized floating-point numbers will generated at the multiplier input. The simulation generates two text files called: ieee mult in.txt and ieee mult out.txt. These files respectively capture the input and output floating-point numbers during the course of the test. Synthesis and Implementation The source file ieee mult.vhd is the only file required for synthesis. There are no sub-modules in the design. The VHDL core is designed to be technology independent. However, as a benchmark, synthesis results have been provided for the Xilinx 7-series FPGAs. Synthesis results for other FPGAs and technologies can be provided on request. Resource usage is specified after Place and Route. Copyright 2018 www.zipcores.com Download this IP Core Page 2 of 2