FIR NTAP SYM Generic high-speed FIR Filter with symmetry Rev. 2.0 Key Design Features Block Diagram Synthesizable, Technology independent VHDL IP Core Implemented as a systolic array for speed and scalability 50% less multipliers than a direct-form FIR implementation Support for filters with inverted symmetry such as High-pass, Differentiators and Hilbert Transformers Configurable coefficients, data width and number of taps Symmetric arithmetic rounding limits DC-bias problems Output saturation or wrap modes Figure 1: Symmetrical FIR filter architecture (Simplified) 1 Supports 500 MHz+ sample rates Pin-out Description Applications Pin name I/O Description Active state High-speed filter applications where resources are limited clk in Sampling clock rising edge en in Clock enable high General purpose FIR filters with symmetrical coefficients x in dw-1:0 in Filter input samples data (signed number) Filters that exhibit inverse symmetry in their coefficients such as High-pass, Differentiators and Hilbert transformers y out dw-1:0 out Filter output samples data (signed number) Generic Parameters General Description Generic name Description Type Valid range FIR NTAP SYM is an FIR filter IP Core with symmetrical coefficients and num taps Number of filter integer > 2 an even or odd number of filter taps. The architecture exploits the taps symmetry of the coefficients using half the number of multipliers dw Width of integer 2 compared to a normal FIR implementation. The result is a filter with a input/output data reduced area footprint while still maintaining the capacity for high sample- samples rates. cw Width of integer 2 Organized as a systolic array (Figure 1) the filter is modular and fully coefficients scalable. Mathematically, the filter implements the difference equation: fw Number of integer 0 coefficient fraction (fw < cw) bits y n = h x n h x n1 ... h x nN 0 1 N 32 32 coeff Filter coefficients integer -2 <coeff <2 num taps-1:0 array In the above equation, the input signal is x n , the output signal is y n and USE ROUNDING Use symmetric Boolean TRUE/FALSE h0 to hN represent the filter coefficients. The number N is the filter order, arithmetic rounding the number of filter taps being equal to N +1. As the filter is symmetrical, (not truncate) the coefficient h0 is equal to hN, h1 is equal to hN-1, h2 is equal to hN-2 etc. USE SATURATE Saturate outputs Boolean TRUE/FALSE (not wrap) USE INV SYMMETRY Coefficients have Boolean TRUE/FALSE inverted symmetry USE OPTZERO Optimize for zero- Boolean TRUE/FALSE valued coefficients USE EVEN Specifies an Even Boolean TRUE/FALSE or Odd number of coefficients 1 Xilinx Virtex6 FPGA used as a benchmark Copyright 2013 www.zipcores.com Download this VHDL Core Page 1 of 4FIR NTAP SYM Generic high-speed FIR Filter with symmetry Rev. 2.0 Filter parameters LatTOT is the total latency between the first input sample to enter the filter and the first output sample, Taps is the total number of filter taps, Lat is RND the latency of the rounding block (equal to 2 clock cycles) and Lat is the SAT 2 Filter coefficients are defined as signed fixed-point numbers in cw fw latency of the saturation block (equal to 1 cycle). format where cw is the total number of coefficient bits and fw is the number of bits in the fractional part. In all cases, cw must be at least 2 As an example, consider a 44 tap filter with rounding and saturation bits and fw must be less than cw to accommodate the sign bit. For enabled. The total latency would be : (44/2) + 2 + 1 + 4 = 29 clock cycles. instance, a coefficient in 10 8 format would be arranged as follows: Functional Timing Figure 2 shows a sequence of input samples for a 44 tap filter with rounding and saturation enabled. Output samples appear 29 clock-cycles later. Values are sampled on the rising clock-edge of clk when en is high. The number of bits in the input and output samples is controlled by the parameter dw. Inputs and outputs are signed values (their format is purely relative). Output samples may be truncated to dw bits or rounded depending on the implementation option USE ROUNDING. If the rounding option is selected, then symmetric arithmetic rounding is used. This means that the fraction 0.1000... is added to positive numbers and 0.0111... is added to negative numbers. Note that filters implemented with the rounding option will help to reduce the small amplitude offset introduced at DC (0 Figure 2: FIR filter input/output samples Hz baseband frequency) attributable to rounding error. In addition, the option USE SATURATE determines what will happen if Source File Description the output samples are too large. If the saturate option is enabled, then in the event of an overflow, the output samples will saturate to the largest positive or negative number permitted by dw. With the saturate option All source files are provided as text files coded in VHDL. The following disabled, the output samples will simply wrap around. Note that table gives a brief description of each file. Note that all generic depending on the format of the coefficients and the data width relative to parameters are defined in the package fir ntap sym pack.vhd . the magnitude of the input samples, the filter outputs may not overflow. In this case, the user may not require the saturation logic. Source file Description In the case where the filter coefficients are symmetrical but inverted about the center tap (i.e. h0 = -hN, h1 = -hN-1 etc.) the parameter fir ntap sym pack.vhd Package containing all generic USE INV SYMMETRY must be set. This ensures that the paired taps parameters - including coefficients. are subtracted as opposed to summed. Filters such as High-pass, Differentiators and Hilbert transformers exhibit this property. fir ntap esym mad.vhd Multiply-Add block even sym filter fir ntap esym mad zero.vhd MAD block optimized for zero- Finally, the parameter USE OPTZERO determines whether the design valued coefficients should be optimized for coefficients with a value of zero. This will result in a smaller design overall, but may also limit the best attainable clock fir ntap esym rnd.vhd Rounding block for even sym filter speed. fir ntap esym sat vhd Saturation block for even sym filter fir ntap esym.vhd FIR with even symmetry Filter latency fir ntap osym mad.vhd Multiply-add block odd sym filter fir ntap osym mad zero.vhd Mulltiply-add block optimized for The filter latency depends on whether the filter has an even or odd zero-valued coefficients number of taps. This is specified in the USE EVEN generic parameter. fir ntap osym madl.vhd Multiply-add block (odd tap) When the filter has an even number of taps the latency formula is: fir ntap osym madl zero.vhd Multiply-add block (odd tap) optimized for zero-valued coefficients Lat =Taps/2+Lat + Lat +4 TOT RND SAT fir ntap osym rnd.vhd Rounding block for odd sym filter fir ntap osym sat.vhd Saturation block for odd sym filter When the filter has an odd number of taps the latency formula is: fir ntap osym.vhd FIR with odd symmetry fir ntap sym.vhd Top-level component Lat =(Taps1)/2+ Lat +Lat +6 TOT RND SAT fir ntap sym bench.vhd Top-level test bench 2 The design is supplied with Matlab scripts for the easy generation of coefficient sets using FDAtool. Please see application note: app note zc002.pdf for more details. Copyright 2013 www.zipcores.com Download this VHDL Core Page 2 of 4