I2C MASTER I2C Master Serial Interface Controller Rev. 1.5 Key Design Features Block Diagram Technology independent IP Core for FPGA and ASIC reset Supplied as human readable VHDL (or Verilog) source code mast inst Phillips I2C-bus compliant mast data Intuitive command interface featuring a simple valid-ready mast val handshake protocol Tristate Buffers mast rdy Master instruction FIFO permits buffering of sequential I2C PAD requests clk scl Slave read FIFO permits buffering of slave read data and slave WRITE FIFO I2C MASTER responses CONTROLLER READ FIFO PAD Fully configurable clocking allows Standard (100 kHz), Fast slv inst sda (400 kHz) custom data rates exceeding 20 MHz slv data Configurable setup and hold times on the SDA line relative to slv val the SCL line slv rdy Supports standard 8-bit and 10-bit addressing modes Applications Driving I2C slave devices Figure 1: I2C Master serial controller architecture Inter-chip board-level communications Generic Parameters Standard 2-wire comms between a wide range of I2C peripherals, micro-controllers and COTs ICs Generic name Description Type Valid range Pin-out Description t period SCL clock period (as integer 4 number of system clock cycles) Pin name I/O Description Active state t data su SDA setup/hold time integer 2 clk in Synchronous clock rising edge (as number of system clock cycles) reset in Asynchronous reset low wfifo depth Master instruction integer 2 mast inst 3:0 in Master instruction data write FIFO depth mast data 7:0 in Master I2C data to be data wfifo depth log2 Master instruction integer log2 serialized write FIFO depth log2 (wfifo depth) mast val in Master instruction valid high rfifo depth Slave read data FIFO integer 2 mast rdy out Master instruction ready high depth handshake rfifo depth log2 Slave read data FIFO integer log2 scl i/o I2C bi-directional SCL As per I2C depth log2 (rfifo depth) clock pin specification sda i/o I2C bi-directional SDA As per I2C General Description data pin specification slv inst 3:0 out Slave instruction data The I2C MASTER IP Core is a Philips I2C compliant serial interface slv data 7:0 out Slave I2C data received data controller capable of driving a standard two-wire bus in single-master from slave device mode. The controller receives data and instructions via the master slv val out Slave data valid high instruction interface. These instructions are then processed by the controller state-machine in order to generate the appropriate responses slv rdy in Slave data ready high on the SCL and SDA lines. handshake Likewise, any slave responses on the I2C-bus are captured by the controller and de-serialized for presentation at the slave read data port. Copyright 2016 www.zipcores.com Download this VHDL Core Page 1 of 5 FIFO stage n FIFO stage 0 FIFO stage 1 FIFO stage 1 FIFO stage 0 FIFO stage nI2C MASTER I2C Master Serial Interface Controller Rev. 1.5 The I2C master controller is comprised of three main blocks as described MASTER INSTRUCTION INPUT FORMAT by Figure 1. These blocks are the master instruction write FIFO, the I2C mast inst 3:0 mast data 7:0 Description controller core and the slave read data FIFO. 0000 7:0 : X Don t care RESET The I/O ports SCL and SDA are connected to bi-directional tristate Reset controller to initial buffers. Note that when the I2C controller is inactive, both the SCL and conditions SDA lines will be tristate and as such, these pins should be externally pulled up as per the I2C specification. 0001 7:0 : X Don t care START The SCL clock-period is determined by the the generic parameter: Issue a I2C start command t period. This parameter specifies the SCL period in system clock cycles. (SCL high, SDA falling edge) As an example, if the system clock clk is running at 100MHz and an SCL clock frequency of 100kHz is required (I2C standard mode), a value of 0010 7:0 : X Don t care STOP t period = 1000 should be specified. Issue a I2C stop command In addition, the generic parameter t data su permits the SDA data-line to (SCL high, SDA rising edge) be delayed by n system clock cycles relative to the SCL line. In this way, 0011 7:1 : Slave Address ADDR the SDA setup and hold specification can be modified accordingly. 0 : R/W flag Write an 8-bit slave address Figure 2 demonstrates how the parameters t period and t data su effect the output signals on the I2C-bus. By modifying t data su, the user can 0100 7:0 : Write data WDATA ensure a stable data window during the active-high SCL pulse. Write 8-bit data 0101 7:0 : X Don t care RDATA SCL Read 8-bit slave data t period 0110 7:0 : X Don t care MACK Issue a master ack signal SDA (SDA low, SCL clock pulse) 0111 7:0 : X Don t care NACK Issue a master no-ack signal t data su t data su (SDA high, SCL clock pulse) 1000 7:0 : X Don t care SACK Slave ack (SDA tristate, SCL clock pulse) Figure 2: I2C timing specification Other values 7:0 : X Don t care NULL Master Write FIFO Performs no action (other than filling up the FIFO) Instructions to the I2C master controller are sent via an input FIFO whose depth is determined by the generic parameter wfifo depth. The write As an example, to write two consecutive bytes to a slave device, the FIFO interface operates in accordance with the valid/ready pipeline following sequence of instructions might be be sent to the controller: protocol meaning that instructions and data are written to the FIFO on the 1 rising edge of clk when both mast val and mast rdy are high The write FIFO may be used to queue up a sequence of commands START ADDR + R/W SACK WDATA SACK WDATA SACK STOP while current commands are being processed on the bus. As soon as the write FIFO becomes full then the FIFO will disable the mast rdy signal0001 0011 1000 0100 1000 0100 1000 0010 signifying that further requests are not possible. Likewise, the mast rdy signal will also be disabled if the slave read-data FIFO becomes full. In both situations, no further commands will be accepted by the I2C A consecutive two byte read might be performed as: controller until the FIFOs have emptied. The instructions to the I2C controller are very intuitive and follow the exact START ADDR + R/W SACK WDATA SACK sequence of commands that the user wishes to appear on the I2C bus. 0001 0011 1000 0100 1000 The following table outlines the set of commands accepted by the controller via the master write FIFO: START ADDR + R/W SACK RDATA MACK RDATA NACK STOP0001 0011 1000 0101 0110 0101 0111 0010 Note that the exact sequence of instructions required will depend on the functionality of the slave device that is to be addressed. For this reason, 1 See Zipcores application note: app note zc001.pdf for more there is no restriction in the ordering of instructions. examples of the valid/ready protocol and it s implementation Copyright 2016 www.zipcores.com Download this VHDL Core Page 2 of 5