XY2 SCALER Bilinear Video Scaling Engine Rev. 2.1 Key Design Features Block Diagram Synthesizable, technology independent VHDL IP Core Versatile 24-bit RGB/YCbCr video scaler capable of scaling up or down by any factor. Different pixel formats supported on request 24-bit accumulator with 24-bit scale-pitch in 24 12 format 16 16 Supports all video resolutions between 16x16 and 2 x 2 pixels Fully pipelined architecture with simple flow control Features a 2x2 polyphase filter in the x and y dimensions. Each filter has 16 unique phases or interpolation points Fully programmable filter coefficients to suit the desired application Example bilinear coefficients shipped with the design Output rate is 1 x 24-bit pixel per clock for scaling factors > 1 Generates one scaled output frame for every input frame Figure 1: Video scaler architecture No frame buffer required 1 Supports 250MHz+ operation on basic FPGA devices Pin-out Description Applications Pin name I/O Description Active state clk in Synchronous clock rising edge High quality 24-bit RGB/YCbCr video scaling reset in Asynchronous reset low Conversion of popular video formats to any other resolution scale pitch x 23:0 in 1 / (x scale factor) data such as VGA to XGA, SVGA to HD1080 etc. Specified as an unsigned number in 24 12 format Digital TV set-top boxes and home media solutions scale pitch y 23:0 in 1 / (y scale factor) data Conversion to non-standard video resolutions - e.g. for use in portable devices and flat-panel displays Specified as an unsigned number in 24 12 format Dynamic scaling of video in a window on a frame-by-frame input ppl 15:0 in Number of pixels per line in data basis the source input frame (Specified as an unsigned Picture in Picture (PiP) applications 16-bit number) input lpf 15:0 in Number of lines per frame data in the source input frame Generic Parameters (Specified as an unsigned 16-bit number) Generic name Description Type Valid range output ppl 15:0 in Number of pixels per line in data the scaled output frame 4 16 line width Width of linestores in integer 2 < pixels < 2 (Specified as an unsigned pixels 16-bit number) log2 line width Log2 of linestore width integer log2(line width) output lpf 15:0 in Number of lines per frame data in the scaled output frame (Specified as an unsigned 16-bit number) 1 Xilinx Virtex6 used as a benchmark Copyright 2014 www.zipcores.com Download this VHDL Core Page 1 of 5XY2 SCALER Bilinear Video Scaling Engine Rev. 2.1 As an example, consider the scaling of VGA format video (640x480) to Pin-out Description cont ... XGA format video (1024x768). In this case the scale pitch in the x and y dimensions would be 0.625. As the value must be specified as a 12.12- 12 bit number the actual scale pitch must be multiplied by 2 giving the Pin name I/O Description Active state generic value 2560 . pixin 23:0 in 24-bit pixel in data In addition the user must also specify the exact resolution of the source pixin vsync in Vertical sync in high input frame and the scaled output frame using the parameters: input ppl, (Coincident with first pixel input lpf, output ppl and output lpf. The following tables give a list of of input frame) generic parameters required for the conversion of some example video formats. pixin hsync in Horizontal sync in high (Coincident with first pixel of input line) SCALE UP pixin val in Input pixel valid high Video Video Pitch Pitch I/P I/P O/P O/P IN OUT X Y PPL LPF PPL LPF pixin rdy out Ready to accept input pixel high (Handshake signal) VGA SVGA 3277 3277 640 480 800 600 640x480 800x600 pixout 23:0 out 24-bit pixel out data SVGA XGA 3200 3200 800 600 1024 768 pixout vsync out Vertical sync out high 800x600 1024x768 (Coincident with first pixel of output frame) XGA HD1080 2184 2913 1024 768 1920 1080 1024x768 1920x1080 pixout hsync out Horizontal sync out high (Coincident with first pixel SXGA 2K 2560 3884 1280 1024 2048 1080 of output line) 1280x1024 2048x1080 pixout val out Output pixel valid high pixout rdy in Ready to accept output high SCALE DOWN pixel Video Video Pitch Pitch I/P I/P O/P O/P (Handshake signal) IN OUT X Y PPL LPF PPL LPF SVGA VGA 5120 5120 800 600 640 480 800x600 640x480 General Description XGA SVGA 5243 5243 1024 768 800 600 1024x768 800x600 XY2 SCALER is a very high quality video scaler capable of generating 16 16 interpolated output images from 16x16 up to 2 x 2 pixels in resolution. HD1080 XGA 7680 5760 1920 1080 1024 768 The architecture permits seamless scaling (either up or down) depending 1920x1080 1024x768 on the chosen scale factor. Internally, the scaler uses a 24-bit 2K SXGA 6554 4320 2048 1080 1280 1024 accumulator and a bank of polyphase FIR filters with 16 phases or 2048x1080 1280x1024 interpolation points. All filter coefficients are programmable, allowing the user to define a wide range of filter characteristics. Flow control Pixels flow in and out of the scaling engine in accordance with the valid- ready pipeline protocol. Pixels are transferred into the scaler on a rising clock-edge when pixin val is high and pixin rdy is high. Likewise, pixels Pixels flow in and out of the scaling engine in accordance with the valid- are transferred out of the scaler on a rising clock-edge when pixout val is 2 ready pipeline protocol . The scaling operation occurs on a line-by-line high and pixout rdy is high. As such, the pipeline protocol allows both basis with the signal pixin hsync specifying the start of a new line and input and output interfaces to be stalled independently. pixin vsync specifying the start of a new frame. All pixels into the scaler The scaler is partitioned into a horizontal scaling section in series with a (including pixin vsync and pixin hsync) must be qualified by the pixin val signal asserted high, otherwise changes to the input signals will be vertical scaling section as shown by Figure 1. ignored. Note that the first pixel of a new frame is accompanied by a valid vsync and hsync. The first pixel in a new line is accompanied by hsync only. Scale pitch, pixels per line and lines per frame On receipt of the first vsync, the scaling operation begins and output pixels are generated in accordance with the chosen scale parameters. The output resolution of the scaled output image is controlled by the Generally, for scale-down (decimation) operations, the input interface will generic parameters scale pitch x, scale pitch y, input ppl, input lpf, not stall. Conversely, for scale-up (interpolation) the number of output output ppl and output lpf. The scale pitch may be calculated using the following formula: pixels will be greater than the number of input pixels. This will result in the occasional stalling of the input due to the change in ratio. Input resolution 12 pitch=( ) 2 Output resolution 2 See Zipcores application note: app note zc001.pdf for more examples of how to use the valid-ready pipeline protocol Copyright 2014 www.zipcores.com Download this VHDL Core Page 2 of 5