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DPSYS RF Power Amplifier Precorrection System Rev. 1.1 Key Design Features Block Diagram Synthesizable, technology independent VHDL Core Compensates and corrects the non-linear characteristic of an RF Power Amplifier operating at high power levels Corrects both the PA Gain and Phase responses - sometimes referred to as the (AM-AM) and (AM-PM) characteristics Features a 256 x 32-bit LUT RAM to store the complex coefficients LUT may be initialized at compile time or modified during normal circuit operation Optional UART, I2C or SPI interface to allow easy programming via a microcontroller Suitable for open-loop or closed-loop operation LUT coefficients may be programmed on-the-fly for adaptive precorrection systems Typically recovers up to 20dB in the output spectral shoulders 1 after the RF Power Amplifier stages Suitable for operation at baseband or IF frequencies Pipeline latency of only 8 clock cycles 2 Sample rates in excess of 200 MHz Applications Power amplifier linearization for mobile Base-stations, Broadcasting etc. Precorrection of wide bandwidth signals such as UMTS, WCDMA and OFDM Precorrection of any type of digitally modulated signal where the signal envelope varies and therefore the instantaneous input power Figure 1: Precorrection system architecture 1 Signal improvement will generally depend on how hard the PA is being driven 2 Xilinx Virtex 5 FPGA used as a benchmark Copyright 2012 www.zipcores.com Download this VHDL Core Page 1 of 6DPSYS RF Power Amplifier Precorrection System Rev. 1.1 Figure 1 shows the stages involved in the precorrection pipeline. The Generic Parameters first stage of the pipeline computes the magnitude of the complex input signal. The magnitude serves as an address into a LUT which in turn indexes a pair of complex coefficients (I & Q). The complex input is Generic name Description Type Valid range multiplied by the complex coefficients in order to modify the gain and phase of the input accordingly. Finally the output is truncated and lut addr shl Selects a 16-bit slice integer 0 to 15 clamped to 16-bit precision. of the 32-bit result of the sum of squares 0 = select LSBs 15:0 Input Magnitude calculation (Resultant 16-bit slice used as an input value 15 = select to square root) MSBs 30:15 The PA gain and phase responses are a function of input signal power. Figure 2 shows a simplified PA characteristic of input power vs. gain and input power vs. phase. These plots are commonly known as the AM-AM Pin-out Description and the AM-PM characteristics of the amplifier. Pin name I/O Description Active state clk in Sample clock rising edge reset in Asynchronous reset low en in clock-enable high pre en in Precorrection high = enable enable/disable low = disable lut addr 7:0 in Complex LUT read/write address address lut wdata 31:0 in Complex LUT write data data I = 31:16 , Q = 15:0 lut rdata 31:0 out Complex LUT read data data I = 31:16 , Q = 15:0 lut en in Complex LUT enable high lut wr in Complex LUT write enable high i in 15:0 in In-phase complex input data q in 15:0 in Quadrature complex input data i out 15:0 out In-phase complex output data q out 15:0 out Quadrature complex output data General Description DPSYS is a complete Digital Precorrection (Predistortion) system Figure 2: Simplified AM-AM and AM-PM responses for an RF designed to compensate for the non-linear characteristic of a high-power Power Amplifier RF Amplifier. The system is capable of adjusting both the gain and phase of a complex input signal. This is achieved by means of a complex multiplication of the input with a complex polynomial function stored in the In order to define an inverse characteristic to those shown in Figure 2, LUT. Complex inputs are sampled on the rising edge of clk when en is the complex input magnitude must first be calculated. This gives a high. relative measure of the input power and therefore a relative position on the x-axis for the AM-AM and AM-PM curves. The magnitude of the The LUT contains the inverse PA characteristic and is applied before the complex input is calculated by the formula: amplification stages (either at baseband or IF frequencies). By programming the LUT with the inverse gain/phase PA response, the resultant PA response is linearized. After linearization, the output signal 2 2 is much cleaner with reduced intermodulation distortion. This is most Equ (1) Mag = I Q in in readily observed by the absence of raised shoulders at either side of the signal of interest. This operation is performed in two stages. The first stage computes the The system may be used in open-loop or closed-loop configuration. For sum of squares (SOS) of the complex input generating a 32-bit unsigned open loop operation, the LUT coefficients are static and programmed result. A 16-bit slice of this result is then taken as an input into the during initial setup of the PA precorrection system. For closed-loop square-root function. The slice-bits are selectable using the generic operation, an external circuit may compare the baseband inputs and PA parameter lut addr shl. which may be adjusted (Figure 3) to ensure that outputs and adjust the LUT coefficients dynamically in order to automate the full dynamic range of the LUT is utilized. the linearization process. Copyright 2012 www.zipcores.com Download this VHDL Core Page 2 of 6