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SINCOS X 18-bit Sine/Cosine Function Rev. 1.1 Key Design Features Block Diagram Synthesizable, technology independent VHDL Core Combined functions y = sin(x), y = cos(x) Input range - x Output range -1 y 1 Based on a quadratic polynomial with dynamic coefficients Input values as 18-bit signed fractions in radians Output values as 17-bit signed fractions Accurate to within 0.00017 Figure 1: sincos x function architecture High-speed fully pipelined architecture Tiny implementation General Description Only 5 clock-cycles latency SINCOS X (Figure 1) calculates the sine and cosine of an angle in radians. It has a fully pipelined architecture and uses fixed-point Applications mathematics throughout. Input values are accepted as 18-bit signed values in the range - to . Output values are 17-bit signed values in the range -1 to 1. For input values outside the specified range, sin out defaults to 0 and cos out defaults to -1. Fixed-point mathematics Input and output values are specified in 18 15 format with 1 sign bit, 2 Quadrature signal generation in digital communications integer bits and 15 fraction bits. Output values are in 17 15 format with 1 sign bit, 1 integer bit and 15 fraction bits. Internally, the function uses a Cheaper alternative to using a 65k x 16-bit LUT (128kbytes) nd quarter-wave SIN function core implemented as a 2 order polynomial with dynamic coefficients. Values are sampled on the rising clock-edge of Cheaper alternative to CORDIC clk when en is high. The function has a 5 clock-cycle latency. Pin-out Description Functional Timing Pin name I/O Description Active state Figure 2 demonstrates the computation of y = sin(x) and y = cos(x) where x is respectively 0x04872 and 0x30066 (0.56598 and -1.99689 as a clk in Synchronous clock rising edge decimal fraction). The results for the SIN calculation are 0x044A4 and 0x18B72 (0.53625 and -0.91058 in decimal). For the COS calculation the en in Clock enable high results are 0x06C09 and 0x1CB1B (0.84402 and -0.41324 in decimal). x in 17:0 in Input value in radians data sin out 16:0 out Output value data cos out 16:0 out Output value data Functional Specification Value Type Valid range x in 17:0 18-bit signed fraction in 18 15 format -, Figure 2: Timing waveform for the sincos function sin out 16:0 17-bit signed fraction in 17 15 format -1, 1 Accuracy to within 0.0002 Note that the second value of x is stalled by the clock-enable signal being cos out 16:0 17-bit signed fraction in 17 15 format 0, 1 de-asserted for one clock cycle. In the next cycle, the clock-enable is Accuracy to asserted high and normal operation continues. The function has a within 0.0002 latency of 5 clock cycles as indicated by edge A and B in the timing waveform. Copyright 2012 www.zipcores.com Download this VHDL Core Page 1 of 2SINCOS X 18-bit Sine/Cosine Function Rev. 1.1 Source File Description Synthesis All source files are provided as text files coded in VHDL. The following The source files required for synthesis and the design hierarchy is shown table gives a brief description of each file. below: sincos x.vhd Source file Description sin x.vhd sin x.vhd Quarter-wave SIN function sincos x.vhd Top-level block The VHDL core is designed to be technology independent. However, as a sincos x bench.vhd Top-level test bench benchmark, synthesis results have been provided for the Xilinx Virtex 6 and Spartan 6 FPGA devices. Synthesis results for other FPGAs and technologies can be provided on request. Functional Testing Resource usage is specified after Place and Route. An example VHDL testbench is provided for use in a suitable VHDL VIRTEX 6 simulator. The compilation order of the source code is as follows: Resource type Quantity used Slice register 153 1. sin x.vhd 2. sincos x.vhd Slice LUT 328 3. sincos x bench.vhd Block RAM 0 DSP48 6 The simulation must be run for at least 3 ms during which time an 18-bit input stimulus in the range 0 to 262143 will be generated. The test Occupied slices 101 terminates automatically. Clock frequency (approx) 200 MHz The simulation generates two text files called sincos x in.txt and sincos x out.txt. These files contain the input and output samples SPARTAN 6 captured during the course of the test. The results of the test are shown graphically in Figure 3 below: Resource type Quantity used Slice register 138 Slice LUT 332 Block RAM 0 DSP48 6 Occupied slices 112 Clock frequency (approx) 150 MHz Revision History Revision Change description Date 1.0 Initial revision 04/05/2009 1.1 Updated synthesis results for Xilinx 6 07/06/2012 series FPGAs Figure 3: Plot of test results for sincos x function Note the valid input range from - to . Values outside this range default to 0 for sin(x) and -1 for cos(x). Copyright 2012 www.zipcores.com Download this VHDL Core Page 2 of 2