VID TIMING GEN Video Timing Generator Rev. 1.5 Key Design Features Block Diagram Synthesizable, technology independent IP Core for FPGA, underflow ASIC and SoC reset Supplied as human readable VHDL (or Verilog) source code dw*3 pix pixin (RGB) vsync Simple FIFO input interface pixin vsync hsync pixin hsync FRAME ASYNC val Programmable RGB channel data width (8,10,12,14-bits etc.) SYNC pixin val FIFO rdy LOGIC pixin rdy Highly versatile architecture supports direct connection to a clk a wide range of video DACs, video encoders and DVI/HDMI transmitters dw*3 pix rdy clk b dw VSYNC, HSYNC, CSYNC, DE and BLANKING outputs vid r dw vid g h s, h bp, h fp, Fully programmable timing parameters dw h disp, vid b h line Supports industry standard (VESA, CEA-861, ITU-R BT.656 vid vsync n v s, v bp, v fp, VIDEO etc.) and fully custom video modes (both progressive and vid hsync n TIMING v disp, TIMING interlaced formats) PARAMS vid csync n v frame CONTROL 16 16 vid vblank Future-proof design supports resolutions up to 2 x 2 pixels vi s, vi bp, vi fp, vi disp, vid hblank (8K video and above) vi frame vid cblank Independent system and pixel clocks supporting frequencies of vid data en 1 400 MHz+ on basic FPGA platforms Compatible with all Zipcores video IP Cores intl start field Applications Figure 1: Video timing generator architecture HD, UHD and SUHD next generation digital video General Description Legacy (SD) and analogue video applications Computer monitors and flat-panel displays The VID TIMING GEN IP Core is a fully configurable video timing 16 16 generator with the ability to support any video resolution up to 2 x 2 Digital TV and multimedia solutions pixels in size. The module is compatible with a wide range of video DACs, encoders and transmitters and provides a flexible solution for displaying digital or analogue video on an external TV, monitor or flat Generic Parameters panel display. The module is capable of clock speeds in excess of 400 MHz on some FPGA platforms, making it ideal for the latest generation HD and UHD video solutions. Generic name Description Type Valid Range Input pixels and syncs are read on the rising edge of clk a (the system 16 dw Pixel data width integer < 2 clock) when pixin val and pixin rdy are both active high. The input signal pixin vsync is coincident with the first active pixel in a frame and the Pixel data is RGB signal pixin hsync is coincident with the first active pixel in a line. where dw defines the width in bits of (Note that these sync signals should not be confused with true video each colour channel timing signals. Their purpose is to delineate the first pixel in a frame and the first pixel in a line only). After resynchronizing the input pixels to the pixel-clock domain (clk b), the controller locks to the first frame (or field) of video. Once frame-lock is achieved, pixels are supplied on demand to the video timing control unit. This module generates the correct RGB video, sync and blanking information depending on the chosen timing parameters. 1 Xilinx 7-series used as a benchmark Copyright 2019 www.zipcores.com Download this VHDL Core Page 1 of 5VID TIMING GEN Video Timing Generator Rev. 1.5 Pin-out Description Pin-out Description cont ... Pin name I/O Description Active state Pin name I/O Description Active state clk a in System clock rising edge pixin dw*3:0 in RGB input pixel data clk b in Pixel clock rising edge pixin vsync in Vertical sync pulse high (coincident with first pixel reset in Asynchronous reset low of a frame or field) underflow out Indicates pixel underflow High pixin hsync in Horizontal sync pulse high (synchronized to clk b) (coincident with first pixel of a line) pixin val in Input pixel valid high intl in Select progressive or 0 = progressive interlaced video 1 = interlaced pixin rdy out Ready to accept input pixel high (handshake signal) start field in Start generating interlaced 0 = ODD video on ODD or EVEN 1 = EVEN field vid r dw - 1:0 out Video out RED data vid g dw - 1:0 out Video out GREEN data h s 15:0 in Horizontal sync pulse data duration vid b dw - 1:0 out Video out BLUE data h bp 15:0 in Horizontal data vid vsync n out Video VSYNC low back-porch duration vid hsync n out Video HSYNC low h fp 15:0 in Horizontal data vid csync n out Video CSYNC low front-porch duration vid vblank out Video vertical BLANK high h disp 15:0 in Active pixels per line data vid hblank out Video horizontal BLANK high h line 15:0 in Duration of whole line data vid cblank out Video composite BLANK high vid data en out Video DATA enable high v s 15:0 in Vertical sync pulse data duration (frame or interlaced field 1) Programmable timing parameters v bp 15:0 in Vertical back-porch data duration (frame or interlaced field 1) The timing parameters determine the duration of the output video, syncs and blanking. They also determine the relative position of the active v fp 15:0 in Vertical front-porch data video signal between syncs. Timing parameters are specified as an duration (frame or integer number of pixels (or pixel clocks) for the horizontal timing. For the interlaced field 1) vertical timing parameters, values are specified as an integer number of v disp 15:0 in Active lines per frame (or data lines. interlaced field 1) Note that the video timing generator also supports interlaced video v frame 15:0 in Duration of whole frame (or data formats. For interlaced formats then the signal intl must be set to true. interlaced field 1) The input signal start field determines whether the output video begins on field 1 or field 2. 2 vi s 15:0 in Vertical sync pulse data When operating in interlaced mode, then the user must specify the duration (interlaced field vertical timing information for both fields. Typically, the first field has 2) fewer vertical blanking lines than the second field. When working with progressive video, then the user only needs to specify the vertical timing vi bp 15:0 in Vertical back-porch data information for a complete frame. The interlaced timing parameters may duration (interlaced field be tied off to zero. 2) vi fp 15:0 in Vertical front-porch data All timing parameters are programmable. Whenever the timing duration (interlaced field parameters are changed during operation, it is advised to reset the 2) module in order to prevent corruption of the video signal. vi disp 15:0 in Active lines per interlaced data The timing parameters must be specified correctly for the chosen video field 2 mode. Figures 2 and 3 on the following page shows this pictorially. vi frame 15:0 in Duration of whole data interlaced field 2 2 Vertical timing parameters for the interlaced field (vi * etc.) are ignored and may be tied to zero when generating progressive video. Copyright 2019 www.zipcores.com Download this VHDL Core Page 2 of 5