SKU64 Zipcores

BT 656 DECODER BT.656 Decoder with Colour-Space Converter Rev. 1.4 Key Design Features Block Diagram Synthesizable, technology independent VHDL Core Converts industry standard BT.656 digital video to 24-bit RGB Integrated 4:2:2 YCbCr to RGB888 colour-space converter Both PAL and NTSC (576i and 480i) input formats supported All signals synchronous with the pixel clock Small implementation size ideal for all types of FPGA Compatible with a wide range of SD video decoder ICs Applications BT.656 input video capture and processing Figure 1: BT.656 Decoder architecture PAL & NTSC SDTV interlaced format conversion General Description Connectivity with a wide range of commercially available video decoder ICs BT 656 DECODER (Figure 1) is a digital video decoder with integrated Simple and cost-effective method for capturing digital video into colour-space converter. It s function is to extract the valid pixels from a BT.656 video stream and convert them to 24-bit RGB for subsequent your FPGA or ASIC processing. Video decoding begins after reset is de-asserted and on the rising-edge Generic Parameters of clk when the video val signal is asserted high. (The signal video val is a clock-enable signal that enables the sampling and processing of each input byte). Generic name Description Type Valid range Pixels are extracted from the BT.656 input stream and converted to mode Input video mode integer 0: PAL (576i) RGB888 format. These pixels are then presented at the output of the 1: NTSC (480i) decoder together with field and sync flags. All signals are synchronous with the input clock. Pin-out Description The video output from the decoder follows a simple valid-ready streaming protocol that is common to all other Zipcores video IP. Output pixels and flags are sampled on a rising clock-edge when pixout val and pixout rdy are both high. Pin name I/O Description Active state clk in Pixel clock rising edge The decoder features an internal FIFO that is sufficient to buffer two lines of input video. If the pixout rdy signal is de-asserted for more than two reset in Asynchronous reset low lines worth of active pixels then the FIFO will fill to capacity and the overflow out Pixel overflow error high overflow flag will be asserted. In the event of an overflow then the decoder must be reset in order to cleanly re-align to the input video video in 7:0 in BT.656 input video (8-bit) data stream. video val in BT.656 input video valid high Note that the pixout rdy signal may be tied high if it is known that the pixout 23:0 out 24-bit RGB888 pixel data downstream interface can always accept output pixels. pixout field out Field flag 0: odd field 1: even field BT.656 Decoder pixout vsync out Vertical sync out high pixout hsync out Horizontal sync out high The decoder samples the incoming BT.656 input and looks for the first active line in field 0 (odd field). Once this is detected, output pixels are pixout val out Output pixel valid high generated on a line-by-line basis. After all the lines in the odd field have pixout rdy in Ready to accept output high been decoded, operation continues with the decoding of all active lines in pixel (handshake signal) field 1 (even field). The decoder then reverts back to field 0 once again. After a system reset, the decoder will revert to it s initial state and stop generating output pixels. Decoding will then begin again with the first active line of field 0 . Copyright 2014 www.zipcores.com Download this VHDL Core Page 1 of 3BT 656 DECODER BT.656 Decoder with Colour-Space Converter Rev. 1.4 When the generic parameter mode is set to 0 , the decoder expects an 576i interlaced video input with a resolution of 720 x 288 pixels per field. Conversely, when mode is set to 1 then the expected input is (480i) or 1 720 x 240 pixels per field . During blanking periods, no valid output pixels are generated. Decoding is only concerned with extraction of active pixels from the BT.656 video stream. Valid 4:2:2 YCbCr pixels are passed to the Colour-Space Converter module where they are converted to 24-bit RGB. Colour-space converter Chroma values from the input pixels (Cb, Cr) are duplicated every second pixel and then converted to the RGB888 colour-space using the following formulas: R=1.164(Y 16)+ 1.596(Cr128) G=1.164(Y 16)+ 0.813(Cr128)0.391(Cb 128) B= 1.164(Y 16)+ 2.018(Cb128) In addition, the colour-space converter also generates correctly aligned vsync, hsync, field and valid flags. All output flags are qualified by the pixout val signal. The signal pixin field is active for the duration of the field, with 0 Figure 3: Output waveforms showing the start of a new field and the start indicating an odd field and 1 indicating an even field. The signal of a new line (pixout rdy shown tied high) pixin vsync is coincident with the first pixel of a field - irrespective of whether odd or even. The signal pixin hsync is coincident with the first pixel of a line. Example timing waveforms are given in the functional Source File Description timing section below. All source files are provided as text files coded in VHDL. The following table gives a brief explanation of each file. Functional Timing Figure 2 shows the input BT.656 video stream into the decoder. Bytes Source file Description are sampled on a rising clock-edge when video val is active high. When bt 656 in.txt BT.656 input video text file (8-bit) video val is low then the input bytes are ignored by the decoder. pipeline reg.vhd Pipeline register element fifo sync.vhd Synchronous FIFO bt 656 file reader.vhd BT.656 text file reader bt 656 dec.vhd Main decoder component bt 656 dec csc.vhd Colour-space converter bt 656 decoder.vhd Top-level component bt 656 decoder bench.vhd Top-level testbench Figure 2: BT.656 input video timing Example output decoder waveforms are shown in Figure 3. Output pixels Functional Testing and syncs are transferred on a rising clock-edge when pixout val and pixout rdy are both high. When pixout val is low then the outputs should be ignored. An example VHDL testbench is provided for use in a suitable VHDL simulator. The compilation order of the source code is as follows: Note that during an active line, the output valid flag will have a 50% duty cycle. This is due to the fact that two bytes must be read from the stream for every generated output pixel. 1. pipeline reg.vhd 2. fifo sync.vhd 3. bt 656 dec csc.vhd 4. bt 656 dec.vhd 5. bt 656 decoder.vhd 6. bt 656 decoder bench.vhd 7. bt 656 file reader.vhd 1 Auto detect of the input video mode is an option. Please contact Zipcores for more information. Copyright 2014 www.zipcores.com Download this VHDL Core Page 2 of 3